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2012-07-13Provide function name in 'Cannot select' fatal error.Jim Grosbach
When dumping the DAG for a fatal 'Cannot select' back-end error, also provide the name of the function the construct is in. Useful when dealing with large testcases, as the next step is to llvm-extract the function in question to get a small(er) testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12The end of the prologue should be marked with is_stmt.Eric Christopher
Fixes PR13303. Patch by Paul Robinson! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160148 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12TableGen: Assembly matcher 'insufficient operands' diagnostic.Jim Grosbach
Make sure the tblgen'erated asm matcher correctly returns numoperands+1 as the ErrorInfo when the problem was that there weren't enough operands specified. rdar://9142751 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160144 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12Fix check strings in test/MC/Disassembler/Mips/* and run FileCheck.Akira Hatanaka
Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160143 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12Fixed few warnings.Galina Kistanova
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160142 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12Give the rdrand instructions a SideEffect flag and a chain so MachineCSE and ↵Benjamin Kramer
MachineLICM don't touch it. I already had the necessary things in place for IR-level passes but missed the machine passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160137 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12Regenerate.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12The LIT tests below do not specify the exact cpu model and fail on AVX2 ↵Nadav Rotem
machines, because we select different instructions such as vbroadcast, new shuffles, etc. Patch by Michael Liao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160129 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12detabifyGabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160128 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12fix typo in generated commentGabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160127 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12llvm/test/CodeGen/X86/rdrand.ll: Relax expression corresponding to Win64 CC.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160124 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12llvm/test/CMakeLists.txt: Add llvm-diff to deps.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160123 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12Use %s instead of the explicit name, the latter doesn't work in out-of-tree ↵Benjamin Kramer
builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160120 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12Add intrinsics for Ivy Bridge's rdrand instruction.Benjamin Kramer
The rdrand/cmov sequence is the same that is emitted by both GCC and ICC. Fixes PR13284. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160117 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12The result type of EXTRACT_VECTOR_ELT doesn't have to match the element type ofDuncan Sands
the input vector, it can be bigger (this is helpful for powerpc where <2 x i16> is a legal vector type but i16 isn't a legal type, IIRC). However this wasn't being taken into account by ExpandRes_EXTRACT_VECTOR_ELT, causing PR13220. Lightly tweaked version of a patch by Michael Liao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12Update GATHER instructions to support 2 read-write operands. Patch from ↵Craig Topper
myself and Manman Ren. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12Instcombine was transforming:Evan Cheng
%shr = lshr i64 %key, 3 %0 = load i64* %val, align 8 %sub = add i64 %0, -1 %and = and i64 %sub, %shr ret i64 %and to: %shr = lshr i64 %key, 3 %0 = load i64* %val, align 8 %sub = add i64 %0, 2305843009213693951 %and = and i64 %sub, %shr ret i64 %and The demanded bit optimization is actually a pessimization because add -1 would be codegen'ed as a sub 1. Teach the demanded constant shrinking optimization to check for negated constant to make sure it is actually reducing the width of the constant. rdar://11793464 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12TableGen: Location information for diagnostic.Jim Grosbach
def Pat<...>; Results in 'record name is not a string!' diagnostic. Not the best, but the lack of location information moves it from not very helpful into completely useless. We're in the Record class when throwing the error, so just add the location info directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160098 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11ARM: fix typo in commentsManman Ren
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160093 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11ARM: Fix optimizeCompare to correctly check safe condition.Manman Ren
It is safe if CPSR is killed or re-defined. When we are done with the basic block, check whether CPSR is live-out. Do not optimize away cmp if CPSR is live-out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160090 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Patch for Mips direct object generation.Jack Carter
When WriteFragmentData() case FT_align called Asm.getBackend().writeNopData() is called, nothing is done since Mips implementation of writeNopData just returned "true". For some reason this has not caused problems in 32 bit mode, but in 64 bit mode it caused an assert when processing multiple function units. The test case included will assert without this patch. It runs twice with different flags to prevent false positives due to changes in code generation over time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160084 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Fixup broken doc link. Patch by Sean Silva <silvas@purdue.edu>.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160082 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11This change removes an "initialization" warning.Jack Carter
Even though variable in question could not be initialized before use, the code was such that the compiler had no way of knowing that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160081 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Fixed diff comparison.Stepan Dyatkovskiy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11In MemoryBuffer::getOpenFile() don't verify that the mmap'edArgyrios Kyrtzidis
file buffer is null-terminated. If the file is smaller than we thought, mmap will not allow dereferencing past the pages that are enough to cover the actual file size, even though we asked for a larger address range. rdar://11612916 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11In register classes in MipsRegisterInfo.td, list the registers in ascendingAkira Hatanaka
order of binary encoding. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160073 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11[x86 fast-isel] Per discussion with Eric, add all cases to switch with verboseChad Rosier
comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160069 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Test case for r160036.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160067 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11X86: Update to peephole optimization to move Movr0 before (Sub, Cmp) pair.Manman Ren
When Movr0 is between sub and cmp, we move Movr0 before sub if it enables removal of Cmp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160066 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11InstrEmitter::EmitSubregNode() optimize extract_subreg in this case:Evan Cheng
r1025 = s/zext r1024, 4 r1026 = extract_subreg r1025, 4 to a copy: r1026 = copy r1024 This is correct. However it uses TII->isCoalescableExtInstr() which can return true for instructions which essentially does a sext_in_reg so this can end up with an illegal copy where the source and destination register classes do not match. Add a check to avoid it. Sorry, no test case possible at this time. rdar://11849816 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11PR13326: Fix a subtle edge case in the udiv -> magic multiply generator.Benjamin Kramer
This caused 6 of 65k possible 8 bit udivs to be wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160058 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11test commitTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160056 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11[x86 fast-isel] Rather then call llvm_unreachable() have fast-isel fall backChad Rosier
to Selection DAG isel. Patch by Andrew Kaylor <andrew.kaylor@intel.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160055 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11When ext-loading and trunc-storing vectors to memory, on x86 32bit systems, ↵Nadav Rotem
allow loads/stores of 64bit values from xmm registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160044 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Rename many of the Tmp1, Tmp2, Tmp3 variables to names such as Chain, Value, ↵Nadav Rotem
Ptr, etc. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160042 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Remove unused variable.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160040 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Refactor the DAG Legalizer by extracting the legalization ofNadav Rotem
Load and Store nodes into their own functions. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160037 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Only apply the SETCC+SITOFP -> SELECTCC optimization when the SETCC returns ↵Owen Anderson
an MVT::i1, i.e. before type legalization. This is a speculative fix for a problem on Mips reported by Akira Hatanaka. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160036 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11Lower RETURNADDR node in Mips backend.Akira Hatanaka
Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160031 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10 Mips specific inline asm operand modifier 'L'.Jack Carter
Low order register of a double word register operand. Operands are defined by the name of the variable they are marked with in the inline assembler code. This is a way to specify that the operand just refers to the low order register for that variable. It is the opposite of modifier 'D' which specifies the high order register. Example: main() { long long ll_input = 0x1111222233334444LL; long long ll_val = 3; int i_result = 0; __asm__ __volatile__( "or %0, %L1, %2" : "=r" (i_result) : "r" (ll_input), "r" (ll_val)); } Which results in: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -8 addu $2, $2, $25 sw $2, 0($sp) lui $2, 13107 ori $3, $2, 17476 <-- Low 32 bits of ll_input lui $2, 4369 ori $4, $2, 8738 <-- High 32 bits of ll_input addiu $5, $zero, 3 <-- Low 32 bits of ll_val addiu $2, $zero, 0 <-- High 32 bits of ll_val #APP or $3, $4, $5 <-- or i_result, high 32 ll_input, low 32 of ll_val #NO_APP addiu $sp, $sp, 8 jr $ra If not direction is done for the long long for 32 bit variables results in using the low 32 bits as ll_val shows. There is an existing bug if 'L' or 'D' is used for the destination register for 32 bit long longs in that the target value will be updated incorrectly for the non-specified part unless explicitly set within the inline asm code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Require and preserve LoopInfo for early if-conversion.Jakob Stoklund Olesen
It will surely be needed by heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Teach the LiveInterval::join function to use the fast merge algorithm,Chandler Carruth
generalizing its implementation sufficiently to support this value number scenario as well. This cuts out another significant performance hit in large functions (over 10k basic blocks, etc), especially those with "natural" CFG structures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160026 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Run early if-conversion in domtree post-order.Jakob Stoklund Olesen
This ordering allows nested if-conversion without using a work list, and it makes it possible to update the dominator tree on the fly as well. Any erased basic blocks will always be dominated by the current post-order position, so the domtree can be pruned without invalidating the iterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Move [get|set]BasePtrStackAdjustment() from MachineFrameInfo toChad Rosier
X86MachineFunctionInfo as this is currently only used by X86. If this ever becomes an issue on another arch (e.g., ARM) then we can hoist it back out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160009 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Add newline.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160006 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Add test case accidentally omitted from r160002.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160004 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier
X86. Basically, this is a reapplication of r158087 with a few fixes. Specifically, (1) the stack pointer is restored from the base pointer before popping callee-saved registers and (2) in obscure cases (see comments in patch) we must cache the value of the original stack adjustment in the prologue and apply it in the epilogue. rdar://11496434 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Fix a bug where I didn't test for an empty range before inspecting theChandler Carruth
back of it. I don't have anything even remotely close to a test case for this. It only broke two build bots, both of them doing bootstrap builds, one of them a dragonegg bootstrap. It doesn't break for me when I bootstrap either. It doesn't reproduce every time or on many machines during the bootstrap. Many thanks to Duncan Sands who got the exact command (and stage of the bootstrap) which failed on the dragonegg bootstrap and managed to get it to trigger under valgrind with debug symbols. The fix was then found by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159993 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Improve the loading of load-anyext vectors by allowing the codegen to loadNadav Rotem
multiple scalars and insert them into a vector. Next, we shuffle the elements into the correct places, as before. Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the migration of bitcasts happened too late in the SelectionDAG process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159991 91177308-0d34-0410-b5e6-96231b3b80d8
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