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2012-07-18test commitVictor Oliveira
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160438 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Add some missed ELF constants definitions:Simon Atanasyan
- section types - dynamic table entries tags - state flags for DT_FLAGS_1 entry The patch reviewed by Rafael Espindola. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160433 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Update config.h.cmake corresponding to config.h.in.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160431 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18The vbroadcast family of instructions has 'fallback patterns' in case where theNadav Rotem
load source operand is used by multiple nodes. The v2i64 broadcast was emulated by shuffling the two lower i32 elements to the upper two. We had a bug in the immediate used for the broadcast. Replacing 0 to 0x44. 0x44 means [01|00|01|00] which corresponds to the correct lane. Patch by Michael Kuperstein. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160430 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Mips specific inline asm operand modifier 'M':Jack Carter
Print the high order register of a double word register operand. In 32 bit mode, a 64 bit double word integer will be represented by 2 32 bit registers. This modifier causes the high order register to be used in the asm expression. It is useful if you are using doubles in assembler and continue to control register to variable relationships. This patch also fixes a related bug in a previous patch: case 'D': // Second part of a double word register operand case 'L': // Low order register of a double word register operand case 'M': // High order register of a double word register operand I got 'D' and 'M' confused. The second part of a double word operand will only match 'M' for one of the endianesses. I had 'L' and 'D' be the opposite twins when 'L' and 'M' are. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160429 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18SCEVTraversal: Add a visited set.Andrew Trick
Expression trees may be DAGs. Make sure traversal has linear complexity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160426 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Remove tab characters.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160425 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Fix typo in error message and remove some tab characters.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160423 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18indvars: drive by heuristics fix.Andrew Trick
Minor oversight noticed by inspection. Sorry no unit test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160422 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18indvars: Linear function test replace should avoid reusing undef.Andrew Trick
Fixes PR13371: indvars pass incorrectly substitutes 'undef' values. I do not like this fix. It's needed until/unless the meaning of undef changes. It attempts to be complete according to the IR spec, but I don't have much confidence in the implementation given the difficulty testing undefined behavior. Worse, this invalidates some of my hard-fought work on indvars and LSR to optimize pointer induction variables. It results benchmark regressions, which I'll track internally. On x86_64 no LTO I see: -3% huffbench -3% 400.perlbench -8% fhourstones My only suggestion for recovering is to change the meaning of undef. If we could trust an arbitrary instruction to produce a some real value that can be manipulated (e.g. incremented) according to non-undef rules, then this case could be easily handled with SCEV. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160421 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper
instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Fixed few warnings.Galina Kistanova
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160419 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18ignore 'invoke @llvm.donothing', but still keep the edge to the continuation BBNuno Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160411 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18More replacing of target-dependent intrinsics with target-indepdent Joel Jones
intrinsics. The second instruction(s) to be handled are the vector versions of count set bits (ctpop). The changes here are to clang so that it generates a target independent vector ctpop when it sees an ARM dependent vector bits set count. The changes in llvm are to match the target independent vector ctpop and in VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM dependent vector pop counts with target-independent ctpops. There are also changes to an existing test case in llvm for ARM vector count instructions and to a test for the bitcode upgrade. <rdar://problem/11892519> There is deliberately no test for the change to clang, as so far as I know, no consensus has been reached regarding how to test neon instructions in clang; q.v. <rdar://problem/8762292> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160410 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Apparently it's possible to do an 'invoke asm'.Nuno Lopes
Update the language reference to reflect that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160408 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Clean up Mips16InstrFormats.td and Mips16InstrInfo.td.Akira Hatanaka
Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160403 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Add test case for r160387Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160389 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Back out r160101 and instead implement a dag combine to recover from ↵Evan Cheng
instcombine transformation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160387 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17TableGen: Pattern<> references to null_frag are a nop.Jim Grosbach
A standalone pattern defined in a multiclass expansion should handle null_frag references just like patterns on instructions. Follow-up to r160333. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160384 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Fix broken ipo_ext_iterator constructors.Jakob Stoklund Olesen
These functions have obviously never been used before. They should be identical to the idf_ext_iterator counterparts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160381 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Add some trace output to TwoAddressInstructionPass.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160380 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Remove unused variable.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160372 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17simplify getSetSize() per Duncan's commentsNuno Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160368 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17llvm/test/Transforms/LoopRotate/PhiRename-1.ll: FileCheck-ize. It fixes PR13301.NAKAMURA Takumi
It began choking since Chandler's r159547, possibly due to improper expression on grep from TclParser to ShParser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160367 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Allow for customized graph edge pruning in PostOrderIterator.hJakob Stoklund Olesen
Make it possible to prune individual graph edges from a post-order traversal by specializing the po_iterator_storage template. Previously, it was only possible to prune full graph nodes. Edge pruning makes it possible to remove loop back-edges, for example. Also replace the existing DFSetTraits customization hook with a po_iterator_storage method for observing the post-order. DFSetTraits was only used by LoopIterator.h which now provides a po_iterator_storage specialization. Thanks to Sean and Chandler for reviewing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Improve behavior of DebugInfoEntryMinimal::getSubprogramName() introduced in ↵Alexey Samsonov
r159512. To fetch a subprogram name we should not only inspect the DIE for this subprogram, but optionally inspect its specification, or its abstract origin (even if there is no inlining), or even specification of an abstract origin. Reviewed by Benjamin Kramer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160365 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17[asan] more code to merge crash callbacks. Doesn't fully work yet, but ↵Kostya Serebryany
allows to hold performance experiments git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160361 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Fix a crash in the legalization of large vectors.Nadav Rotem
When truncating a result of a vector that is split we need to use the result of the split vector, and not re-split the dead node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160357 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Implement r160312 as target indepedenet dag combine.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160354 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Revert commit r160307. We decide to move builtins selection to the backend.Simon Atanasyan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160352 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Make sure constant bitwidth is <= 64 bit before calling getSExtValue().Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160350 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17This is another case where instcombine demanded bits optimization createdEvan Cheng
large immediates. Add dag combine logic to recover in case the large immediates doesn't fit in cmp immediate operand field. int foo(unsigned long l) { return (l>> 47) == 1; } we produce %shr.mask = and i64 %l, -140737488355328 %cmp = icmp eq i64 %shr.mask, 140737488355328 %conv = zext i1 %cmp to i32 ret i32 %conv which codegens to movq $0xffff800000000000,%rax andq %rdi,%rax movq $0x0000800000000000,%rcx cmpq %rcx,%rax sete %al movzbl %al,%eax ret TargetLowering::SimplifySetCC would transform (X & -256) == 256 -> (X >> 8) == 1 if the immediate fails the isLegalICmpImmediate() test. For x86, that's immediates which are not a signed 32-bit immediate. Based on a patch by Eli Friedman. PR10328 rdar://9758774 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Reapply r160340. LSR: Limit CollectSubexprs.Andrew Trick
Speculatively fix crashes by code inspection. Can't reproduce them yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160344 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Revert "LSR: try not to blow up solving combinatorial problems brute force."Andrew Trick
Some units tests crashed on a different platform. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160341 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17LSR: try not to blow up solving combinatorial problems brute force.Andrew Trick
This places limits on CollectSubexprs to constrains the number of reassociation possibilities. It limits the recursion depth and skips over chains of nested recurrences outside the current loop. Fixes PR13361. Although underlying SCEV behavior is still potentially bad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17TableGen: Allow conditional instruction pattern in multiclass.Jim Grosbach
Define a 'null_frag' SDPatternOperator node, which if referenced in an instruction Pattern, results in the pattern being collapsed to be as-if '[]' had been specified instead. This allows supporting a multiclass definition where some instaniations have ISel patterns associated and others do not. For example, multiclass myMulti<RegisterClass rc, SDPatternOperator OpNode = null_frag> { def _x : myI<(outs rc:), (ins rc:), []>; def _r : myI<(outs rc:), (ins rc:), [(set rc:, (OpNode rc:))]>; } defm foo : myMulti<GRa, not>; defm bar : myMulti<GRb>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160333 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Fix function select_cc_f32 in test/CodeGen/Mips/selectcc.ll.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160329 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Defer checking for registers in the MC AsmMatcher until the after ↵Owen Anderson
user-defined match classes have been checked. This allows the creation of MatchClass's that are supersets of a register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160327 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16fix PR13339 (remove the predecessor from the unwind BB when removing an invoke)Nuno Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160325 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16teach ConstantRange that zero times X is always zeroNuno Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160317 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16For something likeEvan Cheng
uint32_t hi(uint64_t res) { uint_32t hi = res >> 32; return !hi; } llvm IR looks like this: define i32 @hi(i64 %res) nounwind uwtable ssp { entry: %lnot = icmp ult i64 %res, 4294967296 %lnot.ext = zext i1 %lnot to i32 ret i32 %lnot.ext } The optimizer has optimize away the right shift and truncate but the resulting constant is too large to fit in the 32-bit immediate field. The resulting x86 code is worse as a result: movabsq $4294967296, %rax ## imm = 0x100000000 cmpq %rax, %rdi sbbl %eax, %eax andl $1, %eax This patch teaches the x86 lowering code to handle ult against a large immediate with trailing zeros. It will issue a right shift and a truncate followed by a comparison against a shifted immediate. shrq $32, %rdi testl %edi, %edi sete %al movzbl %al, %eax It also handles a ugt comparison against a large immediate with trailing bits set. i.e. X > 0x0ffffffff -> (X >> 32) >= 1 rdar://11866926 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Minor cleanup and docs.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160311 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16MIPS: Create two definitions for __builtin_mips_shll_qb builtin.Simon Atanasyan
The first variant accepts immediate number as the second argument. The second variant accepts register operand as the second argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160307 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Make ComputeDemandedBits return a deterministic result when computing an ↵Nadav Rotem
AssertZext value. In the added testcase the constant 55 was behind an AssertZext of type i1, and ComputeDemandedBits reported that some of the bits were both known to be one and known to be zero. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160305 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard
This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "include/llvm: Add R600 Intrinsics v6"Tom Stellard
This reverts commit 600f7a90f3eef4c5108179b43e27cfd9e5de7cdc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160302 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "Build script changes for R600/SI Codegen v6"Tom Stellard
This reverts commit e3013202259ed1e006c21817c63cf25d75982721. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "test/CodeGen/R600: Add some basic tests v6"Tom Stellard
This reverts commit 11d3457afcda7848448dd7f11b2ede6552ffb9ea. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160300 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, ↵Tom Stellard
<llvm/IRBuilder.h> and <llvm/TypeBuilder.h>" This reverts commit 0258a6bdd30802f5cc0e8e57c8e768fde2aef590. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add ↵Tom Stellard
AMDGPUCommonTableGen." This reverts commit ebc934ba32ee71abbb8f0f2eb6a0fbaa613ba0d2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160298 91177308-0d34-0410-b5e6-96231b3b80d8
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