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2011-12-15Don't try to form FGETSIGN after legalization; it is possible in some cases, ↵Eli Friedman
but the existing code can't do it correctly. PR11570. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15Use SmallVector/assign(), rather than std::vector/push_back().Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146627 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15Add support for lowering fneg when AVX is enabled.Chad Rosier
rdar://10566486 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15Added InstCombine for "select cond, ~cond, x" type patternsPete Cooper
These can be reduced to "~cond & x" or "~cond | x" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146624 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. ↵Owen Anderson
These are already marked as illegal by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146623 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15Make loop preheader insertion in LoopSimplify handle the case where the loop ↵Eli Friedman
header is a landing pad correctly (by splitting the landingpad out of the loop header). Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads. PR11575. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146621 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15Re-re-enable compact unwind after fixing a failure in ↵Bill Wendling
SingleSource/Benchmarks/Shootout-C++/except.cpp and friends. It was encoding the stored registers in the wrong order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146617 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15Another improvement to the implementation of .incbin directive by avoiding aKevin Enderby
buffer copy. Suggestion by Chris Lattner! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146614 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14The saved registers weren't being processed in the correct order. This lead toBill Wendling
the compact unwind claiming that one register was saved before another, which isn't all that great in general. Process them in the natural order. Reverse the list only when necessary for the algorithm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146612 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Move Instruction::isSafeToSpeculativelyExecute out of VMCore andDan Gohman
into Analysis as a standalone function, since there's no need for it to be in VMCore. Also, update it to use isKnownNonZero and other goodies available in Analysis, making it more precise, enabling more aggressive optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146610 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Consider CPE alignment in CreateNewWater().Jakob Stoklund Olesen
An aligned constant pool entry may require extra alignment padding where the new water is created. Take that into account when computing offset. Also consider the alignment of other constant pool entries when splitting a basic block. Alignment padding may make it necessary to move the split point higher. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146609 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14ARM NEON better assembly operand range checking for lane indices of VLD/VST.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146608 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Do not sink instruction, if it is not profitable.Devang Patel
On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. Radar 10266272. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146604 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Add a blurb about MachineInstr bundling support.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146603 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Reapply r146481 with a fix to create the Builder value in the correct place andBill Wendling
with the correct iterator. <rdar://problem/10530851> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146600 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Improve the implementation of .incbin directive by replacing a loop by usingKevin Enderby
getStreamer().EmitBytes. Suggestion by Benjamin Kramer! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146599 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14LSR: Fold redundant bitcasts on-the-fly.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146597 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14ARM NEON fix alignment encoding for VST2 w/ writeback.Jim Grosbach
Add tests for w/ writeback instruction parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Add the .incbin directive which takes the binary data from a file and emitsKevin Enderby
it to the streamer. rdar://10383898 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Nuke old code. Missed in last commit.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Add high level description of MachineInstr bundles.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14ARM NEON refactor VST2 w/ writeback instructions.Jim Grosbach
In addition to improving the representation, this adds support for assembly parsing of these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146588 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14ARM NEON improve factoring a bit. No functional change.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Model ARM predicated write as read-mod-write. e.g.Evan Cheng
r0 = mov #0 r0 = moveq #1 Then the second instruction has an implicit data dependency on the first instruction. Sadly I have yet to come up with a small test case that demonstrate the post-ra scheduler taking advantage of this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14ARM NEON VST2 assembly parsing and encoding.Jim Grosbach
Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Fix for bug #11429: Wrong behaviour for switches. Small improvement for code ↵Stepan Dyatkovskiy
size heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14It turns out that clang does use pointer-to-function types toDan Gohman
point to ARC-managed pointers sometimes. This fixes rdar://10551239. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146577 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Fix speling and 80-col.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct objectAkira Hatanaka
emission is not supported yet, but a patch that adds the support should follow soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146572 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Fix copy/pasto that skipped the 'modify' step.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146571 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14ARM/Thumb2 mov vs. mvn alias goes both ways.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146570 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14VFP2 is required for FP loads. Noticed by inspection.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Tidy up.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14ARM/Thumb2 'cmp rn, #imm' alias to cmn.Jim Grosbach
When 'cmp rn #imm' doesn't match due to the immediate not being representable, but 'cmn rn, #-imm' does match, use the latter in place of the former, as it's equivalent. rdar://10552389 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Fix 80-column violation and extraneous brackets.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146566 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Vectors are not aggregate types (see isAggregateType).Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146561 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14llvm/lib/CodeGen: Fix cmake build since r146542.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146550 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Fix a stupid typo in MemDepPrinter.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146549 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Add missing cases to SDNode::getOperationName(). Patch by Micah Villmow.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146548 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Allow target to specify register output dependency. Still default to one.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146547 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Revert r146481 to review possible miscompilations.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146546 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Disable to review some failures.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146545 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14ARM assembler support for the target-specific .req directive.Jim Grosbach
rdar://10549683 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146543 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Add newline at EOF.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146538 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14DW_AT_virtuality is also defined to be constant, not flag.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146534 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14Per discussion on the list, remove BitcodeVerify pass to reimplement as a ↵Chad Rosier
free function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146531 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14[asan] remove .preinit_array from the compiler module (it breaks .so ↵Kostya Serebryany
builds). This should be done in the run-time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146527 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13llvm-nm: refactor in order to support reading files from stdin.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146524 91177308-0d34-0410-b5e6-96231b3b80d8
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