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2012-10-11Expose move to/from coprocessor instructions in MIPS64 mode.David Chisnall
Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a custom CP2 that interprets instructions differently and may wish to add their own instructions that use this opcode. We should ensure that this is easy to do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this easy: We want to avoid the GCC situation where every MIPS vendor makes a custom fork that breaks every other MIPS CPU and so can't be merged upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165711 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11llvm/Analysis/Passes.h: Fix copypasto in createDependenceAnalysisPass().NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165709 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11dependence analysisSebastian Pop
Patch from Preston Briggs <preston.briggs@gmail.com>. This is an updated version of the dependence-analysis patch, including an MIV test based on Banerjee's inequalities. It's a fairly complete implementation of the paper Practical Dependence Testing Gina Goff, Ken Kennedy, and Chau-Wen Tseng PLDI 1991 It cannot yet propagate constraints between coupled RDIV subscripts (discussed in Section 5.3.2 of the paper). It's organized as a FunctionPass with a single entry point that supports testing for dependence between two instructions in a function. If there's no dependence, it returns null. If there's a dependence, it returns a pointer to a Dependence which can be queried about details (what kind of dependence, is it loop independent, direction and distance vector entries, etc). I haven't included every imaginable feature, but there's a good selection that should be adequate for supporting many loop transformations. Of course, it can be extended as necessary. Included in the patch file are many test cases, commented with C code showing the loops and array references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Follow the same routine to add target float expansion hookMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165707 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11misched: Handle "transient" non-instructions.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165701 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Don't crash when !tbaa.struct contents is invalid.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165693 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Revert r165661, "Patch by Shuxin Yang <shuxin.llvm@gmail.com>."NAKAMURA Takumi
It broke stage2 clang and test-suite/MultiSource/Benchmarks/mediabench/g721/g721encode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165692 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11GettingStarted.rst: s/&amp;/&/gNAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165690 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11GettingStarted.rst: Fix the label to DeveloperPolicy.html.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165689 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Add the LLVM context to this c'tor. It will be needed in the future.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Support a common idiom on how to build an Attributes class with a single ↵Bill Wendling
attribute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165686 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Don't crash if a .ll file contains a forward-reference that looks like a globalNick Lewycky
value but later turns out to be a function. Unfortunately, we can't fold tests into a single file because we only get one error out of llvm-as. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165680 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Change MachineInstrBuilder::addDisp to copy over target flags by default.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165677 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add isel patterns for v2f32 / v4f32 neon.vbsl intrinsics. rdar://12471808Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165673 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add getters for the MIPS TargetTransform classesNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165670 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Remove unused member variable introduced in r165665.David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165669 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Formatting and 80-col.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165668 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add -mattr=+altivec and remove XFAIL.Bill Schmidt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165666 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add a new interface to allow IR-level passes to access codegen-specific ↵Nadav Rotem
information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10XFAIL for all targets pending investigationBill Schmidt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Patch by Shuxin Yang <shuxin.llvm@gmail.com>.Nadav Rotem
Original message: The attached is the fix to radar://11663049. The optimization can be outlined by following rules: (select (x != c), e, c) -> select (x != c), e, x), (select (x == c), c, e) -> select (x == c), x, e) where the <c> is an integer constant. The reason for this change is that : on x86, conditional-move-from-constant needs two instructions; however, conditional-move-from-register need only one instruction. While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase. The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165661 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10When generating spill and reload code for vector registers on PowerPC,Bill Schmidt
the compiler makes use of GPR0. However, there are two flavors of GPR0 defined by the target: the 32-bit GPR0 (R0) and the 64-bit GPR0 (X0). The spill/reload code makes use of R0 regardless of whether we are generating 32- or 64-bit code. This patch corrects the problem in the obvious manner, using X0 and ADDI8 for 64-bit and R0 and ADDI for 32-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10The PowerPC VRSAVE register has been somewhat of an odd beast sinceBill Schmidt
the Altivec extensions were introduced. Its use is optional, and allows the compiler to communicate to the operating system which vector registers should be saved and restored during a context switch. In practice, this information is ignored by the various operating systems using the SVR4 ABI; the kernel saves and restores the entire register state. Setting the VRSAVE register is no longer performed by the AIX XL compilers, the IBM i compilers, or by GCC on Power Linux systems. It seems best to avoid this logic within LLVM as well. This patch avoids generating code to update and restore VRSAVE for the PowerPC SVR4 ABIs (32- and 64-bit). The code remains in place for the Darwin ABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165656 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add in support for expansion of all of the comparison operations to the ↵Micah Villmow
absolute minimum required set. This allows a backend to expand any arbitrary set of comparisons as long as a minimum set is supported. The minimum set of required instructions is ISD::AND, ISD::OR, ISD::SETO(or ISD::SETOEQ) and ISD::SETUO(or ISD::SETUNE). Everything is expanded into one of two patterns: Pattern 1: (LHS CC1 RHS) Opc (LHS CC2 RHS) Pattern 2: (LHS CC1 LHS) Opc (RHS CC2 RHS) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Revert r165652: "Remove unnecessary RTTI from the build."Sean Silva
... Apparently the RTTI is still necessary for some reason. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Remove unnecessary RTTI from the build.Sean Silva
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165652 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10tblgen: Compile TableGen without RTTI.Sean Silva
TableGen no longer needs RTTI! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10tblgen: Move mini Type hierarchy to LLVM-style RTTI.Sean Silva
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165648 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10tblgen: Use semantically correct RTTI functions.Sean Silva
Also, some minor cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165647 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva
Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10tblgen: Put dyn_cast<> machinery in place for Init hierarchy.Sean Silva
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165645 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add the testcase from pr13254 (the old scalarreply pass handles this wrong;Duncan Sands
the new sroa pass handles it right). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165644 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Remove dead variable.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165639 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Specify CPU model to avoid breaking ATOM buildsMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165638 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Remove unused argument.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165636 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10docs: Propagate fix from r165632 to other docs.Sean Silva
There are only two other instances of using `.. code::` instead of `.. code-block::`. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165633 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10docs: Attempt to fix PR14053.Sean Silva
Hypothesis 1: use of `.. code::` directive instead of `.. code-block::` is causing Sphinx to discard the block. On my machine, `.. code::` renders fine. However, I don't think that `.. code::` is actually a legit Sphinx directive. I believe that on my machine Sphinx is falling back to just displaying it monospace with no syntax, whereas llvm.org's Sphinx is just discarding it. This is truly "remote debugging" since I can't reproduce this on my machine. It would be helpful to be able to see the llvm.org Sphinx build logs; if that's possible please let me know. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add support for FP_ROUND from v2f64 to v2f32Michael Liao
- Due to the current matching vector elements constraints in ISD::FP_ROUND, rounding from v2f64 to v4f32 (after legalization from v2f32) is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPROUND to work around this constraints. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165631 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add alternative support for FP_ROUND from v2f32 to v2f64Michael Liao
- Due to the current matching vector elements constraints in ISD::FP_EXTEND, rounding from v2f32 to v2f64 is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPEXT to work around this constraints. This patch also reverts a previous attempt to fix this issue by recovering the scalarized ISD::FP_EXTEND pattern and thus significantly reduces the overhead of supporting non-power-2 vector FP extend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10[CMake] check-all: Don't include check-llvm into check-all without ↵NAKAMURA Takumi
LLVM_BUILD_TOOLS. FIXME: Would you like to run llvm/unittests w/o LLVM_BUILD_TESTS regardless of LLVM_BUILD_TOOLS? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165619 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10[CMake] add_lit_testsuite: EXCLUDE_FROM_ALL excludes the test ${target} out ↵NAKAMURA Takumi
of check-all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165618 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Fix for LDRB instruction:Stepan Dyatkovskiy
SDNode for LDRB_POST_IMM is invalid: number of registers added to SDNode fewer that described in .td. 7 ops is needed, but SDNode with only 6 is created. In more details: In ARMInstrInfo.td, in multiclass AI2_ldridx, in definition _POST_IMM, offset operand is defined as am2offset_imm. am2offset_imm is complex parameter type, and actually it consists from dummy register and imm itself. As I understood trick with dummy reg was made for AsmParser. In ARMISelLowering.cpp, this dummy register was not added to SDNode, and it cause crash in Peephole Optimizer pass. The problem fixed by setting up additional dummy reg when emitting LDRB_POST_IMM instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165617 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Issue description:Stepan Dyatkovskiy
SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack objects and byval parameters. So loading byval parameters from stack may be inserted *before* it will be stored, since these operations are treated as independent. Fix: Currently ARMTargetLowering::LowerFormalArguments saves byval registers with FixedStack MachinePointerInfo. To fix the problem we need to store byval registers with MachinePointerInfo referenced to first the "byval" parameter. Also commit adds two new fields to the InputArg structure: Function's argument index and InputArg's part offset in bytes relative to the start position of Function's argument. E.g.: If function's argument is 128 bit width and it was splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index, but different offset values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165616 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Cleanup. Get rid of now dead code.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165613 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Remove the final bits of Attributes being declared in the AttributeBill Wendling
namespace. Use the attribute's enum value instead. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10My earlier "fix" for PBQP (see r165201) was incorrect. The real issue was thatLang Hames
checkRegMaskInterference only initializes the bitmask on the first interference. This fixes PR14027 and (re)fixes PR13945. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165608 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Pass into the AttributeWithIndex::get method an ArrayRef of attributeBill Wendling
enums. These are then created via the correct Attributes creation method. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165607 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10misched: fall-back to a target hook for instr bundles.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165606 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10TODO commentAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165605 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10TableGen subtarget emitter cleanup.Andrew Trick
Consistently evaluate Aliases and Sequences recursively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165604 91177308-0d34-0410-b5e6-96231b3b80d8
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