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2003-05-29Doxygenify commentsChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6393 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29When TableGen finds an error in the SparcV9.td file, it exits with a non-zeroMisha Brukman
exit code. This, in turn, makes an empty file SparcV9CodeEmitter.inc, and only much later, produces a link error because the key function that TableGen creates isn't found. Using a temporary file in the middle forces a good .INC file to be generated by TableGen, and it will keep trying until you fix the input file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6392 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29Fixed misspelling and broke a line that was wrapping.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6391 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29Fixed to use the correct format of the instruction.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6390 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29This should work better with re-generating the SparcV9CodeEmitter.inc file.Misha Brukman
Also, added a rule to delete the generated .inc file on `make clean'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6389 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29* Broke up SparcV9.td into separate files as it was getting unmanageableMisha Brukman
* Added some Format 4 classes, but not instructions * Added notes on missing sections with FIXMEs * Added RDCCR instr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6388 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-28mmap() seems to be failing on Sparc, so just use malloc()/free() .Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6387 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-28Output the opcode name of the instruction being emitted to cerr.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6386 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-28Correctly write out binary data as chars, before they're cast to ints.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6385 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-28Fixed ordering of elements in instructions: although the binary instructionsMisha Brukman
list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is instr rd, imm, rs1, and that is how they are constructed in the instruction selector. This fixes the discrepancy. Also fixed some comments along the same lines and fixed page numbers referring to where instructions are described in the Sparc manual. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6384 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-28Add dependency to make TableGen rule fire.Brian Gaeke
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6383 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-28Three kinds of boolean values handled incorrectly:Vikram S. Adve
-- setCC of FP type used by a Phi: have to save in reg. -- setNE of FP type used by a branch: cannot use result directly in branch! -- setCC used outside the same basic block: have to save in reg. for now git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6382 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Fixed an error preventing compilation.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6381 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Added the 'r' and 'i' annotations to instructions as their opcode names haveMisha Brukman
changed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6380 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Added a debugging code emitter that prints code to a file, debug to std::cerr,Misha Brukman
and passes the real code to a memory-outputting code emitter. This may be removed at a later point in development. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6379 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Keep track of the current BasicBlock being processed so that a referencingMisha Brukman
MachineInstr can later be patched up correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6378 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Added 'r' and 'i' annotations to instructions as SparcInstr.def has changed.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6377 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.Misha Brukman
Non-obvious change: since I have changed ST and STD to be STF and STDF to (a) closer resemble their name (NOT assembly text) in the Sparc manual, and (b) clearly specify that they they are floating-point opcodes, I made the same changes in this file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6376 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.Misha Brukman
Here I had to make one non-trivial change: add a function to get a version of the opcode that takes an immediate, given an opcode that takes all registers. This is required because sometimes it is not known at construction time which opcode is used because opcodes are passed around between functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6375 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6373 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Added entries for each of the instructions with annotations ('r' or 'i').Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6372 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27One of the first major changes to make the work of JITting easier: addingMisha Brukman
annotations on instructions to specify which format they are (i.e., do they take 2 registers and 1 immediate or just 3 registers) as that changes their binary representation and hence, code emission. This makes instructions more like how X86 defines them to be. Now, writers of instruction selection must choose the correct opcode based on what instruction type they are building, which they already know. Thus, the JIT doesn't have to do the same work by `discovering' which operands an instruction really has. As this involves lots of small changes to a lot of files in lib/target/Sparc, I'll commit them individually because otherwise the diffs will be unreadable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6371 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Cannot output `static' in generated cpp code: results in error. It's alreadyMisha Brukman
specified as a static member in class definition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6370 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27* Allow passing in an unsigned configuration to allocateSparcTargetMachine()Misha Brukman
a default value is set in the header file. * Fixed some code layout to make it more consistent with the rest of codebase * Added addPassesToJITCompile() with relevant passes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6369 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27* Now outputting a static function getBinaryCodeForInstr() (JIT-accessible)Misha Brukman
* For debugging purposes: + output the predefined bit pattern of the instruction * Fixed inefficiency: only load an operand from MachineInstr once * Bug fix: did not advance bit index when seeing named bit-fields "annul", "cc" and "predict" * Added a catch-all for non-supported instructions at the end of switch stmt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6368 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Moved generation of the SparcV9CodeEmitter.inc file higher in the Makefile soMisha Brukman
that Makefile.common would see it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6367 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Add prototypes to add passes to JIT compilation and code emission.Misha Brukman
Also, added annotations to how instructions are modified (reg/imm operands). Added prototype for adding register numbers to values pass for interfacing with the target-independent register allocators in the JIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6366 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Defines a pass-through debugging emitter -- it writes to a file for inspectionMisha Brukman
and to memory to test execution (using a passed-in code emitter). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6365 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Allow allocation of a Sparc TargetMachine.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6364 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Broke out class definition from SparcV9CodeEmitter, and added ability to take aMisha Brukman
MachineCodeEmitter to make a pass-through debugger -- output to memory and to std::cerr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6363 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Update to match the reality that is now.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6362 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Link in Sparc libs for the JIT, even on X86 to be able to support debuggingMisha Brukman
of Sparc JIT (printing out instrs) on X86. Con: this increases linking time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6361 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Allow for specification of which JIT to run on the commandline.Misha Brukman
`lli -march=x86' or `lli -march=sparc' will forcefully select the JIT even on a different platform. Running lli without the -march option will select the JIT for the platform that it's currently running on. Pro: can test Sparc JIT (debug printing mode) on X86 -- faster to compile/link LLVM source base to test changes. Con: Linking lli on x86 now pulls in all the Sparc libs -> longer link time (but X86 can bear it, right?) In the future, perhaps this should be a ./configure option to enable/disable target JITting... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6360 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Remove ugly hack (that I put in originally) for building in trace stuffChris Lattner
automatically in LLC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6358 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27SparcV9CodeEmitter.cpp is a part of the Sparc code emitter. The main functionMisha Brukman
that assembles instructions is generated via TableGen (and hence must be built before building this directory, but that's already the case in the top-level Makefile). Also added is .cvsignore to ignore the generated file `SparcV9CodeEmitter.inc', which is included by SparcV9CodeEmitter.cpp . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6357 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Added definitions for a bunch of floating-point instructions.Misha Brukman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6356 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Fix constant folding to ALWAYS work.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6355 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Add compatibility optionChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6354 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27New testcaseChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6353 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Fix bug: Instcombine/2003-05-27-ConstExprCrash.llChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6352 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Make _sure_ we don't go into an infinite loop if a signal happens!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6351 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Start testing SRoAChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6350 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27* Actually USE the statistic that we madeChris Lattner
* Implement SRoA for arrays git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6349 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Expose proto for SRoA pass.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6348 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Initial testcases for scalar replacement of aggregates passChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6347 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Implementation of the simple "scalar replacement of aggregates" transformationChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6346 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27(1) Added special register class containing (for now) %fsr.Vikram S. Adve
Fixed spilling of %fcc[0-3] which are part of %fsr. (2) Moved some machine-independent reg-class code to class TargetRegInfo from SparcReg{Class,}Info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6343 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()Vikram S. Adve
and related functions and flags. Fixed several bugs where only "isDef" was being checked, not "isDefAndUse". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6342 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27(1) Added special register class containing (for now) %fsr.Vikram S. Adve
Fixed spilling of %fcc[0-3] which are part of %fsr. (2) Moved some machine-independent reg-class code to class TargetRegInfo from SparcReg{Class,}Info. (3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly() and related functions and flags. Fixed several bugs where only "isDef" was being checked, not "isDefAndUse". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6341 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27Renamed opIsDef to opIsDefOnly.Vikram S. Adve
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6340 91177308-0d34-0410-b5e6-96231b3b80d8