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2013-04-16simplifycfg: Fix integer overflow converting switch into icmp.Hans Wennborg
If a switch instruction has a case for every possible value of its type, with the same successor, SimplifyCFG would replace it with an icmp ult, but the computation of the bound overflows in that case, which inverts the test. Patch by Jed Davis! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179587 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16Add 64-bit multiply and divide instructions for SPARC v9.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179582 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15ARM: Add VACLT and VACLE assembly aliases.Jim Grosbach
These are aliases for VACGT and VACGE, respectively, with the source operands reversed. rdar://13638090 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179575 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15We are not able to bitcast a pointer to an integral value.Bill Wendling
Two return types are not equivalent if one is a pointer and the other is an integral. This is because we cannot bitcast a pointer to an integral value. PR15185 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Mips assembler: Explicit floating point condition register recognition.Jack Carter
This patch allows the assembler to recognize $fcc0 as a valid register for conditional move instructions. Corresponding test cases have been added. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Fix a grammar mistake, and add a line about the two phases that the BB/SLP ↵Nadav Rotem
vectorizers have (top-down and bottom-up). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179566 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Fix the internal link.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179565 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Update the release notes about the vectorizers.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179564 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15SLPVectorizer: Make it a function pass and add code for hoisting the ↵Nadav Rotem
vector-gather sequence out of loops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179562 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Fix silly typo that broke big endian hosts.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179551 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Fix endianness on some MSVC versions.Rafael Espindola
Looks like it was evaluating undef == undef to true. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179549 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15R600/SI: Emit config values in register value pairs.Tom Stellard
Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15R600/SI: Emit configuration value in the .AMDGPU.config ELF sectionTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179545 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15R600: Emit ELF formatted code rather than raw ISA.Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179544 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Fix a typo in comment.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179542 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Simplify the MCInst operator iterator declaration.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179541 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Grammar and punctuation fixes.John Criswell
No content changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179540 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Try to fix the mingw builds.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179536 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Fix bit size of v64i8 and v32i16 vector types.Arnold Schwaighofer
Patch by Cameron McInally <cameron.mcinally@nyu.edu>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179535 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Remove getters now that we can specialize structs on the host endianness.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179534 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Avoid outputting temporary test file into source tree.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179532 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Remove unused function.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179530 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Make the host endianness check an integer constant expression.Rafael Espindola
I will remove the isBigEndianHost function once I update clang. The ifdef logic is designed to * not use configure/cmake to avoid breaking -arch i686 -arch ppc. * default to little endian * be as small as possible It looks like sys/endian.h is the preferred header on most modern BSD systems, but it is better to change this in a followup patch as machine/endian.h is available on FreeBSD, OpenBSD, NetBSD and OS X. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Replace uses of the deprecated std::auto_ptr with OwningPtr.Andy Gibbs
This is a rework of the broken parts in r179373 which were subsequently reverted in r179374 due to incompatibility with C++98 compilers. This version should be ok under C++98. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179520 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Enable all targets by default on Visual Studio.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179518 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Revert "Recommit r179497 after fixing uninitialized variable." untilEric Christopher
I can fix the testcases here: http://lab.llvm.org:8011/builders/clang-native-arm-cortex-a9/builds/6952 This reverts commit r179512 due to testcases specifying triples that they didn't actually mean and causing failures on other platforms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179513 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Recommit r179497 after fixing uninitialized variable.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179512 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Document our desire to enable the loop vectorizer on -Os in future releases.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179511 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Docs: merge the description of the BB and SLP vectorizers and document the ↵Nadav Rotem
-fslp-vectorize-aggressive flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179510 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Add an option -vectorize-slp-aggressive for running the BB vectorizer. Make ↵Nadav Rotem
-fslp-vectorize run the slp-vectorizer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179508 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Rename the slp-vectorizer clang/llvm flags. No functionality change.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179505 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15SLPVectorizer: Add support for vectorizing trees that start at compare ↵Nadav Rotem
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179504 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15fix include path in doc Extending LLVMJia Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179503 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Mark all PPC comparison instructions as not having side effectsHal Finkel
Now that the CR spilling issues have been resolved, we can remove the unmodeled-side-effect attributes from the comparison instructions (and also mark them as isCompare). By allowing these, by default, to have unmodeled side effects, we were hiding problems with CR spilling; but everything seems much happier now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179502 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Fix PPC64 CR spill location for callee-saved registersHal Finkel
This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition registers, the spill location is specified relative to the stack pointer (SP + 8). However, this is not relative to the SP after the new stack frame is established, but instead relative to the caller's stack pointer (it is stored into the linkage area of the parent's stack frame). So, like with the link register, we don't directly spill the CRs with other callee-saved registers, but just mark them to be spilled during prologue generation. In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179500 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Revert "Remove some unused triple and data layout."Eric Christopher
This reverts commit r179497 and the accompanying commit as it broke random platforms that aren't osx. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179499 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Remove some unused triple and data layout.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179498 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14If we've specified a triple on the command line then go aheadEric Christopher
and use that as the default triple for the module and target data layout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179497 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Use object file specific section type for initial text sectionNico Rieck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Reorders two transforms that collide with each otherDavid Majnemer
One performs: (X == 13 | X == 14) -> X-13 <u 2 The other: (A == C1 || A == C2) -> (A & ~(C1 ^ C2)) == C1 The problem is that there are certain values of C1 and C2 that trigger both transforms but the first one blocks out the second, this generates suboptimal code. Reordering the transforms should be better in every case and allows us to do interesting stuff like turn: %shr = lshr i32 %X, 4 %and = and i32 %shr, 15 %add = add i32 %and, -14 %tobool = icmp ne i32 %add, 0 into: %and = and i32 %X, 240 %tobool = icmp ne i32 %and, 224 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179493 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Make the command line triple match the module triple.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179492 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Miscellaneous cleanups for VecUtils.hBenjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179483 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Document the SLP infrastructure.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179480 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14SLP: Document the scalarization cost method.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179479 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Document the decision to assume that the cost of floats is twice as much as ↵Nadav Rotem
integers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179478 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Use i32 for all SPARC shift amounts, even in 64-bit mode.Jakob Stoklund Olesen
Test case by llvm-stress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179477 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Remove unused function attributes.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14SLPVectorizer: Add support for trees that don't start at binary operators, ↵Nadav Rotem
and add the cost of extracting values from the roots of the tree. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179475 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Add support for the abs64 SPARC v9 code model.Jakob Stoklund Olesen
For when 16 TB just isn't enough. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179474 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Add support for the SPARC v9 abs44 code model.Jakob Stoklund Olesen
This is the default model for non-PIC 64-bit code. It supports text+data+bss linked anywhere in the low 16 TB of the address space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179473 91177308-0d34-0410-b5e6-96231b3b80d8
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