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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132751 91177308-0d34-0410-b5e6-96231b3b80d8
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operands to an early clobber register. This fixes <rdar://problem/9566076>.
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Fixes PR10095.
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- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.
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Requested by nbjoerg!
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on CINT2006 for x86-32.
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codegen. Thanks Galina.
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MipsFrameLowering::emitPrologue:
- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
callee-saved register is emitted even when no callee-saved registers are
saved.
- When a callee-saved double precision register is saved, two cfi_offset
directives, one for each of the paired single precision registers, should be
emitted.
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I've been sitting on this long enough trying to find a test case. I
think the fix should go in now, but I'll keep working on the test case.
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rdar://problem/9556069
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When local live range splitting creates a live range with the same
number of instructions as the old range, mark it as RS_Local. When such
a range is seen again, require that it be split in a way that reduces
the number of instructions. That guarantees we are making progress while
still being able to perform 3 -> 2+3 splits as required by PR10070.
This also means that the PrevSlot map is no longer needed. This was also
used to estimate new spill weights, but that is no longer necessary
after slotIndexes::insertMachineInstrInMaps() got the extra Late
insertion argument.
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load. rdar://problem/6373334
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you can just run bugpoint -O2. :) My implementation isn't precisely equivalent to what opt does, but as far as I can tell, it's close enough.
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Only target-dependent hints require callbacks. The RCI allocation order
has CSR aliases last according to their order of appearance in the
getCalleeSavedRegs list. This can depend on the calling convention.
This way, AllocationOrder::next doesn't have to check for reserved
registers, and CSRs are always allocated last, even with weird calling
conventions.
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legalize SDNodes such as BUILD_VECTOR, EXTRACT_VECTOR_ELT, etc.
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it was added, the test has regressed, so XFAIL it.
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The order of registers returned by getCalleeSavedRegs is used to lay out
the fixed stack slots for CSRs. Some targets like their CSRs used from
one end, and some targets want them used from the other end.
When computing an allocation order, simply preserve the relative
ordering of CSRs that the target specifies in its allocation order.
Reordering CSRs would break some targets, ARM in particular.
We still place volatiles before the CSRs, providing slightly better
results with different calling conventions.
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We still don't handle
* default values
* :req
* :vararg
* \()
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VK_GOTOFF reloc. This matches as' behavior, but it is not clear why the linker
might need this, so I added a FIXME.
I could test this by duplicating test/MC/ELF/got.s, but it doesn't look
worthwhile.
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Who said FileCheck couldn't handle arbitrarily complex conditions?
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(copyFromParts/copyToParts).
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(only happens when using the -promote-elements option).
The correct legalization order is to first try to promote element. Next, we try
to widen vectors.
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rules. Also refactor "read string until quote" into its own function. No
functionality change!
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then we don't want to set the destination in the indirect branch to the
destination. This is because the indirect branch needs its destinations to have
had their block addresses taken. This isn't so of the new critical edge that's
split during this process. If it turns out that the destination block has only
one predecessor, and that being a BB with an indirect branch, then it won't be
marked as 'used' and may be removed.
PR10072
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ignored for clobbering partial-alias loads.
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is disabled.
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redundant with partially-aliasing loads.
When computing what portion of a clobbering load value is needed,
it doesn't consider phi-translation which may have occurred
between the clobbing load and the redundant load.
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64bit code for example.
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