aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2012-06-08Teach the AsmMatcherEmitter to allow InstAlias' where the suboperands of a ↵Owen Anderson
complex operand are called out explicitly in the asm string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158183 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07[CMake] Promote extension warnings to errors.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158176 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07X86: optimize generated code for integer ABSManman Ren
This patch will generate the following for integer ABS: movl %edi, %eax negl %eax cmovll %edi, %eax INSTEAD OF movl %edi, %ecx sarl $31, %ecx leal (%rdi,%rcx), %eax xorl %ecx, %eax There exists a target-independent DAG combine for integer ABS, which converts integer ABS to sar+add+xor. For X86, we match this pattern back to neg+cmov. This is implemented in PerformXorCombine. rdar://10695237 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158175 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07[CMake] Order MSVC warnings numerically.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158171 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07[CMake] Adjust MSVC warnings.Michael J. Spencer
Remove /Wall from LLVM_ENABLE_WARNINGS (it's useless) and promote 4239 to a level 1 warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158170 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07Do not optimize the used bits of the x86 vselect condition operand, when the ↵Nadav Rotem
condition operand is a vector of 1-bit predicates. This may happen on MIC devices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158168 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07Fix a bug in FoldSelectOpOp. Bitcast ops may change the number of vector ↵Nadav Rotem
elements, which may disagree with the select condition type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158164 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07ARM getOperandLatency rewrite.Andrew Trick
Match expectations of the new latency API. Cleanup and make the logic consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158163 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07ARM getOperandLatency should return -1 for unknown, consistent with APIAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07Fix ARM getInstrLatency logic to work with the current API.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158161 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07PR13046: we can't replace usage of SUB with CMP in the lowering phase.Manman Ren
It will cause assertion failure later on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158160 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07Use a base register instead of an index register with the local dynamic model.Rafael Espindola
Fixes pr13048. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158158 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07Move terminator machine verification to check ↵Pete Cooper
MachineBasicBlock::instr_iterator instead of MBB::iterator git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07Add internal read flags to MachineInstrBuilder and hook them into the ↵Pete Cooper
MachineOperand flag of the same name git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158137 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07Adding a missing -S to the opt invocation.Meador Inge
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158128 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-07X86: replace SUB with CMP if possibleManman Ren
This patch will optimize the following movq %rdi, %rax subq %rsi, %rax cmovsq %rsi, %rdi movq %rdi, %rax to cmpq %rsi, %rdi cmovsq %rsi, %rdi movq %rdi, %rax Perform this optimization if the actual result of SUB is not used. rdar: 11540023 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158126 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Spell optimization name correclty.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158123 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Revert r157755.Manman Ren
The commit is intended to fix rdar://11540023. It is implemented as part of peephole optimization. We can actually implement this in the SelectionDAG lowering phase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Another testcase for r156548.Bill Wendling
<rdar://problem/10889741> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158121 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06[llvm-nm] Update documentation to cover object file support and arguments.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158120 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Properly verify liveness with bundled machine instructions.Jakob Stoklund Olesen
Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158116 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Add accessors for all private members of DisasmContext.Benjamin Kramer
LLVM should be -Wunused-private-field clean now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158103 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Move RegisterClassInfo.h.Andrew Trick
Allow targets to access this API. It's required for RegisterPressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158102 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Remove dead private member variables from gtest.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Move RegisterPressure.h.Andrew Trick
Make it a general utility for use by Targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158097 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Round 2 of dead private variable removal.Benjamin Kramer
LLVM is now -Wunused-private-field clean except for - lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields. - gtest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158096 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer
There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier
X86. rdar://11496434 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158087 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Fix combine of uno && ord -> false so that the ordering of the fcmps doesn'tChad Rosier
matter. rdar://11579835 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158084 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Remove dead debug option -disable-rematerialization.Jakob Stoklund Olesen
Remat has been stable for years, and it isn't done by LiveIntervalAnalysis any longer. (See LiveRangeEdit). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158079 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Grab-bag of reassociate tweaks. Unify handling of dead instructions andDuncan Sands
instructions to reoptimize. Exploit this to more systematically eliminate dead instructions (this isn't very useful in practice but is convenient for analysing some testcase I am working on). No need for WeakVH any more: use an AssertingVH instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158073 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Stop leaking RegScavengers from TailDuplication.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158069 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Correct decoder for T1 conditional B encodingRichard Barton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158055 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Add a new broken compiler.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158053 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Mark several instructions SSE2 instead of SSE3 as they should be.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Fix gtest build issue on Visual Studio 2012 RCJustin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158046 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06Remove extraneous CHECK-NOTs from previous commit and add a new test case.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158045 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-06FileCheckize this test.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158044 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05Move LiveUnionArray into LiveIntervalUnion.hJakob Stoklund Olesen
It is useful outside RegAllocBase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158041 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05Don't print register names in LiveIntervalUnion::print().Jakob Stoklund Olesen
Soon we'll be making LiveIntervalUnions for register units as well. This was the only place using the RepReg member, so just remove it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158038 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05Suppress -Wunused-variable in -Asserts buildMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158037 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05Simplify LiveInterval::print().Jakob Stoklund Olesen
Don't print out the register number and spill weight, making the TRI argument unnecessary. This allows callers to interpret the reg field. It can currently be a virtual register, a physical register, a spill slot, or a register unit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158031 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05Add experimental support for register unit liveness.Jakob Stoklund Olesen
Instead of computing a live interval per physreg, LiveIntervals can compute live intervals per register unit. This makes impossible the confusing situation where aliasing registers could have overlapping live intervals. It should also make fixed interferernce checking cheaper since registers have fewer register units than aliases. Live intervals for regunits are computed on demand, using MRI use-def chains and the new LiveRangeCalc class. Only regunits live in to ABI blocks are precomputed during LiveIntervals::runOnMachineFunction(). The regunit liveness computations don't depend on LiveVariables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158029 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05Implement LiveRangeCalc::extendToUses() and createDeadDefs().Jakob Stoklund Olesen
These LiveRangeCalc methods are to be used when computing a live range from scratch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05MachineInstr::eraseFromParent fix for removing bundled instrs.Andrew Trick
Patch by Ivan Llopard. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05misched: API for minimum vs. expected latency.Andrew Trick
Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05Add 3.0 and 3.1 tags to the getting started guide.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158020 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05Add a new intrinsic: llvm.fmuladd. This intrinsic represents a multiply-addLang Hames
expression (a * b + c) that can be implemented as a fused multiply-add (fma) if the target determines that this will be more efficient. This intrinsic will be used to implement FP_CONTRACT support and an aggressive FMA formation mode. If your target has a fast FMA instruction you should override the isFMAFasterThanMulAndAdd method in TargetLowering to return true. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-05Fix header file include order in NVPTX backend NV_CONTRIBYuan Lin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158013 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-16 02:34:06 +0000