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2012-01-1080 col violation.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Add missing VEX predicates to VMOVSDto64rr/VMOVSDto64mr. This fixes a fewChad Rosier
failing test cases on our internal AVX nightly tester. rdar://10663637 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147881 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Let asm parser query asm syntax dialect.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147880 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10This is the matching change for the data structure name changes for theKevin Enderby
functional change in r147860 to use DW_TAG_label's instead TAG_subprogram's. This only changes names and updates comments. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10ARM updating VST2 pseudo-lowering fixed vs. register update.Jim Grosbach
rdar://10663487 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147876 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Fix some leftover control reaches end of non-void function warnings.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147874 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Teach the triple library about the androideabi environment.Chandler Carruth
Patch by Evgeniy Stepanov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147871 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Move default case for covered enum outside of switch.Richard Smith
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147870 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10For i386, don't use the generic code.Bill Wendling
As the comment around 7746 says, it's better to use the x87 extended precision here than SSE. And the generic code doesn't know how to do that. It also regains the speed lost for the uint64_to_float.c testcase. <rdar://problem/10669858> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147869 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Fix a -Wreturn-type warning in g++.Richard Smith
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147867 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Cleanup these asserts to follow common LLVM style and codingChandler Carruth
conventions. Also, clarify the grouping of one of the asserts to silence -Wparentheses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147863 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Add 'llvm_unreachable' to passify GCC's understanding of the constraintsChandler Carruth
of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147861 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Various crash reporting tools have a problem with the dwarf generated forKevin Enderby
assembly source when it generates the TAG_subprogram dwarf debug info for the labels that have nothing between them as in this bit of assembly source: % cat ZeroLength.s _func1: _func2: nop One solution would be to not emit the subsequent labels with the same address and use the next label with a different address or the end of the section for the AT_high_pc value of the TAG_subprogram. Turns out in llvm-mc it is not possible in all cases to determine of two symbols have the same value at the point we put out the TAG_subprogram dwarf debug info. So we will have llvm-mc instead of putting out TAG_subprogram's put out DW_TAG_label's. And the DW_TAG_label does not have a AT_high_pc value which avoids the problem. This commit is only the functional change to make the diffs clear as to what is really being changed. The next commit will be to clean up the names of such things like MCGenDwarfSubprogramEntry to something like MCGenDwarfLabelEntry. rdar://10666925 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147860 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Add definition for intel asm variant.Devang Patel
Right now, this just adds additional entries in match table. The parser does not use them yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147859 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Record asm variant id in MatchEntry and check it while matching instruction.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147858 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Remove unnecessary default cases in switches that cover all enum values.David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Fix a bug in the legalization of shuffle vectors. When we emulate shuffles ↵Nadav Rotem
using BUILD_VECTORS we may be using a BV of different type. Make sure to cast it back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Add definitions for AMD's bobcat (aka btver1)Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147846 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Fix a crash in AVX2 when trying to broadcast a double into a 128-bit vector. ↵Craig Topper
There is no vbroadcastsd xmm, but we do need to support 64-bit integers broadcasted into xmm. Also factor the AVX check into the isVectorBroadcast function. This makes more sense since the AVX2 check was already inside. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147844 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Remove hasXMM/hasXMMInt functions. Move callers to hasSSE1/hasSSE2. This is ↵Craig Topper
the final piece to remove the AVX hack that disabled SSE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147843 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Remove hasSSE*orAVX functions and change all callers to use just hasSSE*. ↵Craig Topper
AVX is now an SSE level and no longer disables SSE checks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Instruction selection priority fixes to remove the XMM/XMMInt/orAVX ↵Craig Topper
predicates. Another commit will remove orAVX functions from X86SubTarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147841 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Allow machine-cse to look across MBB boundary when cse'ing instructions thatEvan Cheng
define physical registers. It's currently very restrictive, only catching cases where the CE is in an immediate (and only) predecessor. But it catches a surprising large number of cases. rdar://10660865 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147827 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Enable LSR IV Chains with sufficient heuristics.Andrew Trick
These heuristics are sufficient for enabling IV chains by default. Performance analysis has been done for i386, x86_64, and thumbv7. The optimization is rarely important, but can significantly speed up certain cases by eliminating spill code within the loop. Unrolled loops are prime candidates for IV chains. In many cases, the final code could still be improved with more target specific optimization following LSR. The goal of this feature is for LSR to make the best choice of induction variables. Instruction selection may not completely take advantage of this feature yet. As a result, there could be cases of slight code size increase. Code size can be worse on x86 because it doesn't support postincrement addressing. In fact, when chains are formed, you may see redundant address plus stride addition in the addressing mode. GenerateIVChains tries to compensate for the common cases. On ARM, code size increase can be mitigated by using postincrement addressing, but downstream codegen currently misses some opportunities. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147826 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Accurately model hardware alignment rounding.Jakob Stoklund Olesen
On Thumb, the displacement computation hardware uses the address of the current instruction rouned down to a multiple of 4. Include this rounding in the UserOffset we compute for each instruction. When inline asm is present, the instruction alignment may not be known. Constrain the maximum displacement instead in that case. This makes it possible for CreateNewWater() and OffsetIsInRange() to agree about the valid displacements. When they disagree, infinite looping happens. As always, test cases for this stuff are insane. <rdar://problem/10660175> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147825 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Remove the logging streamer.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147820 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Catch runaway ARMConstantIslandPass even in -Asserts builds.Jakob Stoklund Olesen
The pass is prone to looping, and it is better to crash than loop forever, even in a -Asserts build. <rdar://problem/10660175> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Fix asm string wrt variants.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147805 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Use descriptive variable name and remove incorrect operand number check.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147802 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Adding IV chain generation to LSR.Andrew Trick
After collecting chains, check if any should be materialized. If so, hide the chained IV users from the LSR solver. LSR will only solve for the head of the chain. GenerateIVChains will then materialize the chained IV users by computing the IV relative to its previous value in the chain. In theory, chained IV users could be exposed to LSR's solver. This would be considerably complicated to implement and I'm not aware of a case where we need it. In practice it's more important to intelligently prune the search space of nontrivial loops before running the solver, otherwise the solver is often forced to prune the most optimal solutions. Hiding the chained users does this well, so that LSR is more likely to find the best IV for the chain as a whole. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147801 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Adding collection of IV chains to LSR.Andrew Trick
This collects a set of IV uses within the loop whose values can be computed relative to each other in a sequence. Following checkins will make use of this information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147797 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Split AsmParser into two components - AsmParser and AsmParserVariantDevang Patel
AsmParser holds info specific to target parser. AsmParserVariant holds info specific to asm variants supported by the target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09"Minor LSR debugging stuff"Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147785 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Update language check. Do not ignore DW_LANG_Python.Devang Patel
Patch by Joe Groff! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147781 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Move assert to the right place.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147779 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09InstCombine: Teach foldLogOpOfMaskedICmpsHelper that sign bit tests are bit ↵Benjamin Kramer
tests. This subsumes several other transforms while enabling us to catch more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147777 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Don't rely on the fact that shift values are never very large, and thusChandler Carruth
this substraction will result in small negative numbers at worst which become very large positive numbers on assignment and are thus caught by the <=4 check on the next line. The >0 check clearly intended to catch these as negative numbers. Spotted by inspection, and impossible to trigger given the shift widths that can be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147773 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Cleanup and FileCheck-ize a test.Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147772 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. ↵Craig Topper
Predicate functions have been altered to maintain previous names and behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147770 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Add HasAVX predicate to some of the AVX patterns.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147769 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Reorder a bunch of patterns to put the AVX version first thus giving it ↵Craig Topper
priority over the SSE version. Another step towards trying to remove the AVX hack that disables SSE from X86Subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147768 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Clean up patterns for MOVNT*. Not sure why there were floating point types ↵Craig Topper
on MOVNTPS and MOVNTDQ. And v4i64 was completely missing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147767 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Mark MOVNTI as being supported in SSE2 OR AVX mode. This instruction has no ↵Craig Topper
AVX equivalent so we should use the SSE version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147766 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Move SSE2 logical operations PAND/POR/PXOR/PANDN above SSE1 logical ↵Craig Topper
operations ANDPS/ORPS/XORPS/ANDNPS. This fixes a pattern ordering issue that meant that the SSE2 instructions could never be directly selected since the SSE1 patterns would always match first. This is largely moot with the ExeDepsFix pass, but I'm trying to audit for all such ordering issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147765 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Change some places that were checking for AVX OR SSE1/2 to use ↵Craig Topper
hasXMM/hasXMMInt instead. Also fix one place that checked SSE3, but accidentally excluded AVX to use hasSSE3orAVX. This is a step towards removing the AVX hack from the X86Subtarget.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Don't print an unused label before .cfi_endproc.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147763 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-09Don't disable MMX support when AVX is enabled. Fix predicates for MMX ↵Craig Topper
instructions that were added along with SSE instructions to check for AVX in addition to SSE level. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-08Enable FISTTP* instructions when AVX is enabled.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147758 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-08Tweak my last commit to be less conservative about uses.Benjamin Kramer
We still save an instruction when just the "and" part is replaced. Also change the code to match comments more closely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147753 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-08Don't forget to transfer implicit uses of return instruction.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147752 91177308-0d34-0410-b5e6-96231b3b80d8
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