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2011-08-09clang is the new black.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137187 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Trim an unneeded header.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Promote VMOVS to VMOVD when possible.Jakob Stoklund Olesen
On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For better latency, we also send D-register copies down the NEON pipeline by translating them to vorr instructions. This patch promotes even S-register copies to D-register copies when possible so they can also go down the NEON pipeline. Example: vldr.32 s0, LCPI0_0 loop: vorr d1, d0, d0 loop2: ... vadd.f32 d1, d1, d16 The vorr instruction looked like this after regalloc: %S2<def> = COPY %S0, %D1<imp-def> Copies involving odd S-registers, and copies that don't define the full D-register are left alone. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Tighten operand checking of register-shifted-register operands.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Fix minor typo.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137177 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Tighten operand checking on memory barrier instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137176 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09VMCore/BasicBlock.cpp: Don't assume BasicBlock::iterator might end with a ↵NAKAMURA Takumi
non-PHInode Instruction in successors. Frontends(eg. clang) might pass incomplete form of IR, to step off the way beyond iterator end. In the case I had met, it took infinite loop due to meeting bogus PHInode. Thanks to Jay Foad and John McCall. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Fix whitespace.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137174 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Tighten operand checking on CPS instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Fix an oversight in the FixedLenDecoderEmitter where we weren't correctly ↵Owen Anderson
checking the success result of custom decoder hooks on singleton decodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Representation of 'atomic load' and 'atomic store' in IR.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Create a new register class for the set of all GPRs except the PC. Use it ↵Owen Anderson
to tighten our decoding of BFI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Add v16i16 and v32i8 store patternsBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137166 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Fix 80-column violations.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Add missing file.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137162 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Use fp unpack instructions to unpack int types. Until we have AVX2, thisBruno Cardoso Lopes
is the best we can do for these patterns. This fix PR10554. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137161 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Fix a couple ridiculous copy-paste errors. rdar://9914773 .Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137160 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Add a C interface to PassManagerBuilder. It is missing the addExtensionRafael Espindola
functionality since in the C api a pass is created and added to a pass manager in a single call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137159 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Don't truncate MachO addresses.Jim Grosbach
Assigned symbol addresses get truncated to 32-bits, even on 64-bit platforms. That's obviously bogus. For example, .globl _foo .equ _foo, 0x987654321ULL rdar://9922863 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137158 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09ARM Disassembler: sign extend branch immediates.Benjamin Kramer
Not sure about BLXi, but this is what the old disassembler did. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137156 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Silence an false-positive warning.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Don't generate the old-style disassembler in CMake builds either.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09The new ARM disassembler disassembles "bx lr" as a special BX_ret ↵Benjamin Kramer
instruction so target specific analysis isn't needed anymore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137151 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Don't continue generating the old-style decoder file.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137150 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09ARM fix typo in pre-indexed store lowering.Jim Grosbach
rdar://9915869 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137148 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Attempt to fix CMake build.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137147 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Tighten Thumb1 branch predicate decoding.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137146 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09First draft of the practical guide to atomics.Eli Friedman
This is mostly descriptive of the intended state once atomic load and store have landed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137145 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Replace the existing ARM disassembler with a new one based on the ↵Owen Anderson
FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Put Darwin-specific code inside an __APPLE__ ifdef.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137137 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Revert r137134. It breaks some code as Eli pointed out.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137135 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Print out the variable declaration only if it is a declaration. Otherwise, aBill Wendling
'static' variable will be emitted twice. PR10081 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137134 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Inflate register classes after coalescing.Jakob Stoklund Olesen
Coalescing can remove copy-like instructions with sub-register operands that constrained the register class. Examples are: x86: GR32_ABCD:sub_8bit_hi -> GR32 arm: DPR_VFP2:ssub0 -> DPR Recompute the register class of any virtual registers that are used by less instructions after coalescing. This affects code generation for the Cortex-A8 where we use NEON instructions for f32 operations, c.f. fp_convert.ll: vadd.f32 d16, d1, d0 vcvt.s32.f32 d0, d16 The register allocator is now free to use d16 for the temporary, and that comes first in the allocation order because it doesn't interfere with any s-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137133 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Reapply a more appropriate solution than in r137114. AVX supportsBruno Cardoso Lopes
v4f64 = sitofp v4i32. This fix PR10559. Also add support for v4i32 = fptosi v4f64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137128 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Revert r137114Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09PTX: Add initial support for device function callsJustin Holewinski
- Calls are supported on SM 2.0+ for function with no return values git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Move CalculateRegClass to MRI::recomputeRegClass.Jakob Stoklund Olesen
This function doesn't have anything to do with spill weights, and MRI already has functions for manipulating the register class of a virtual register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Emitting ARM build attributes and values as ULEB, rather than char.Renato Golin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137115 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Handle sitofp between v4f64 <- v4i32. Fix PR10559Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137114 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Recognize the UNAME_RELEASE environment variable to match Darwin's uname.Bob Wilson
When this variable is set, "uname -r" will return its value instead of the real OS version. Make this affect LLVM's triple for consistency. <rdar://problem/9919167> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09LoopUnroll looks like it has some stale code. Remove it to prove my sanity ↵Andrew Trick
and avoid further confusion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Add support for avx vector fextendBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Add AVX versions of 128-bit sitofp and fptosiBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Rename and tidy up testsBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137103 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Add two patterns to match special vmovss and vmovsd cases. Also fixBruno Cardoso Lopes
the patterns already there to be more strict regarding the predicate. This fixes PR10558 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09There is only one instance of this placeholder being created. Just use thatBill Wendling
instead of a vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Remove an instance where the 'unwind' instruction was created.Bill Wendling
The 'unwind' instruction was acting essentially as a placeholder, because it would be replaced at the end of this function by a branch to the "unwind handler". The 'unwind' instruction is going away, so use 'unreachable' instead, which serves the same purpose as a placeholder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Print variable's inline location in debug output.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Provide method to print variable's extended name which includes inline location.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137095 91177308-0d34-0410-b5e6-96231b3b80d8
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