aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2012-05-11Typo.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156633 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11[fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. ↵Chad Rosier
Minor cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Hexagon V5 intrinsics support.Sirish Pande
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156631 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Defer computation of SuperRegs.Jakob Stoklund Olesen
Don't compute the SuperRegs list until the sub-register graph is completely finished. This guarantees that the list of super-registers is properly topologically ordered, and has no duplicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156629 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11[fast-isel] Cleaner fix for when we're unable to handle a non-double multi-regChad Rosier
retval. Hoists check before emitting the call to avoid unnecessary work. rdar://11430407 PR12796 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11objectsize: add a few more tests and fix a bugNuno Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11[fast-isel] Rather then assert (or segfault in a non-asserts build), fall backChad Rosier
to selection DAG isel if we're unable to handle a non-double multi-reg retval. rdar://11430407 PR12796 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11The return type is an unsigned, not a bool.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156621 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Add space before an open parenthesis in control flow statements.Manman Ren
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156620 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156615 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11PR1255: ConstantRangesSet and CRSBuilder classes moved from include/llvm to ↵Stepan Dyatkovskiy
include/llvm/Support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156613 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Fix test/CodeGen/X86/tls-pie.ll.Hans Wennborg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156612 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Implement initial-exec TLS model for 32-bit PIC x86Hans Wennborg
This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong code here (see the update to test/CodeGen/X86/tls-pie.ll). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156611 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Added the missing bit definition for the 4th bit of the STR (post reg) ↵Silviu Baranga
instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate ↵Silviu Baranga
offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156608 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Fix a use after free when the streamer is destroyed. Fixes pr12622.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156606 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Fix a misleading comment.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Tidy up. Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156602 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Tidy up. Trailing whitespace.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156601 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Fix a minor logic mistake transforming compares in instcombine. PR12514.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156600 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11ARM: peephole optimization to remove cmp instructionManman Ren
This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman
but it generates int3 on x86 instead of ud2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-11Allow unique_file to take a mode for file permissions, but defaultEric Christopher
to user only read/write. Part of rdar://11325849 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Fix intendation.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156589 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Compute secondary sub-registers.Jakob Stoklund Olesen
The sub-registers explicitly listed in SubRegs in the .td files form a tree. In a complicated register bank, it is possible to have sub-register relationships across sub-trees. For example, the ARM NEON double vector Q0_Q1 is a tree: Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3] But we also define the DPair register D1_D2 = [D1, D2] which is fully contained in Q0_Q1. This patch teaches TableGen to find such sub-register relationships, and assign sub-register indices to them. In the example, TableGen will create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a sub-register of Q0_Q1. This will eventually enable the coalescer to handle copies of skewed sub-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10objectsize: add support for GEPs with non-constant indexesNuno Lopes
add an additional parameter to InstCombiner::EmitGEPOffset() to force it to *not* emit operations with NUW flag git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156585 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156579 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Add support for the 'X' inline asm operand modifier.Eric Christopher
Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156577 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: Print machineinstrs with -debug-only=mischedAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156576 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: tracing register pressure heuristics.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156575 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick
Prioritize the instruction that comes closest to keeping pressure under the target's limit. Then prioritize instructions that avoid increasing the max pressure in the scheduled region. The max pressure heuristic is a tad aggressive. Later I'll fix it to consider the unscheduled pressure as well. WIP: This is mostly functional but untested and not likely to do much good yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156574 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: Release only unscheduled nodes into ReadyQ.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156573 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156572 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10misched: Introducing Top and Bottom register pressure trackers during ↵Andrew Trick
scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Hexagon V5 Support - V5 td file.Sirish Pande
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Hexagon V5 FP Support.Sirish Pande
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156568 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10RegPressure: API for speculatively checking instruction pressure.Andrew Trick
Added getMaxExcessUpward/DownwardPressure. They somewhat abuse the tracker by speculatively handling an instruction out of order. But it is convenient for now. In the future, we will cache each instruction's pressure contribution to make this efficient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156561 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10RegPressure: fix array index iteration style.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156560 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Teach DeadStoreElimination to eliminate exit-block stores with phi addresses.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156558 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Revert: 156550 "ARM: peephole optimization to remove cmp instruction"Manman Ren
This commit broke an external linux bot and gave a compile-time warning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Precompute lists of explicit sub-registers and indices.Jakob Stoklund Olesen
The .td files specify a tree of sub-registers. Store that tree as ExplicitSubRegs lists in CodeGenRegister instead of extracting it from the Record when needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156555 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Rewrite ScalarEvolution::hasOperand to use an explicit worklist insteadDan Gohman
of recursion, to avoid excessive stack usage on deep expressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156554 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10teach DSE and isInstructionTriviallyDead() about callocNuno Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156553 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10formatting change: strip debug info from testJoel Jones
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156551 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10ARM: peephole optimization to remove cmp instructionManman Ren
This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Fix a problem with incomplete equality testing of PHINodes in Joel Jones
Instruction::IsIdenticalToWhenDefined. This manifested itself when inlining two calls to the same function. The inlined function had a switch statement that returned one of a set of global variables. Without this modification, the two phi instructions that chose values from the branches of the switch instruction inlined from the callee were considered equivalent and jump-threading replaced a load for the first switch value with a phi selecting from the second switch, thereby producing incorrect code. This patch has been tested with "make check-all", "lnt runteste nt", and llvm self-hosted, and on the original program that had this problem, wireshark. <rdar://problem/11025519> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156548 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Fix merge-typo and cleanupNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156541 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10AVX2: Add an additional broadcast idiom.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156540 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Generate AVX/AVX2 shuffles even when there is a memory op somewhere else in ↵Nadav Rotem
the program. Starting r155461 we are able to select patterns for vbroadcast even when the load op is used by other users. Fix PR11900. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156539 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-10Fix TableGen's RegPressureSet weight normalization to handle subreg DAGS.Andrew Trick
I initially assumed that the subreg graph was a tree. That may not be true. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156524 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2025-09-21 23:32:15 +0000