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2012-05-15llvm-config: Use sys::fs::equivalent instead of string comparison.Daniel Dunbar
- Hopefully fixes PR11600 (untested). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156865 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15[Support] Add a version of sys::fs::equivalent() that treats errors as false.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15[docs] Remove unsupported references to ExtraSource variable.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156857 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Add blurb for Crack.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156852 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Add a test case for r156840, a fix to llvm-objdump when disassembling usingKevin Enderby
-macho to disassemble the last symbol to the end of the section. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156850 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15reuse the result of some expensive computations in getSignExtendExpr() and ↵Nuno Lopes
getZeroExtendExpr() this gives a speedup of > 80 in a debug build in the test case of PR12825 (php_sha512_crypt_r) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156849 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Extend the CoalescerPair interface to handle symmetric sub-register copies.Jakob Stoklund Olesen
Now both SrcReg and DstReg can be sub-registers of the final coalesced register. CoalescerPair::setRegisters still rejects such copies because RegisterCoalescer doesn't yet handle them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156848 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Update MIPS' section in the release notes. Patch by Simon Atanasyan.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156847 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Add -enable-aa-sched-mi, off by default, for AliasAnalysis inside ↵Andrew Trick
MachineScheduler. This feature avoids creating edges in the scheduler's dependence graph for non-aliasing memory operations according to whichever alias analysis is available. It has been fully tested in Hexagon. Before making this default, it needs to be extended to handle multiple MachineMemOperands, compile time needs more evaluation, and benchmarking on X86 and ARM is needed. Patch by Sergei Larin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Fixed a bug in llvm-objdump when disassembling using -macho option for a binaryKevin Enderby
that has more than one symbol. The last symbol was not being disassembled to the end of the section. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15llvm-build: Add support for non-installed libraries (e.g., gtest).Daniel Dunbar
- These libraries are only reported by llvm-config when run from a development tree. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156838 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15llvm-build: Don't emit library information for disabled targets.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156837 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15[utils] Fix Get{RepositoryPath,SourceVersion} to have a more robust is-git-svnDaniel Dunbar
check. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156836 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15TableGen'erate mapping physical registers to encoding values.Jim Grosbach
Many targets always use the same bitwise encoding value for physical registers in all (or most) instructions. Add this mapping to the .td files and TableGen'erate the information and expose an accessor in MCRegisterInfo. patch by Tom Stellard. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156829 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Allow MCCodeEmitter access to the target MCRegisterInfo.Jim Grosbach
Add the MCRegisterInfo to the factories and constructors. Patch by Tom Stellard <Tom.Stellard@amd.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156828 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Enable all Hexagon tests.Sirish Pande
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15minor simplification to code: Ty is already a SCEV type; don't need to run ↵Nuno Lopes
getEffectiveSCEVType() twice git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156823 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Add some release notes about compiler-rt and libc++David Chisnall
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Teach SimplifyLibCalls about stpcpy.David Majnemer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156815 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Remove warning about testing unsigned int with int.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156812 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Fixed one small stupid, but critical bug.Stepan Dyatkovskiy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156810 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Rejected r156804 due to buildbots failures.Stepan Dyatkovskiy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156808 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15SelectionDAGBuilder::Clusterify : main functinality was replaced with ↵Stepan Dyatkovskiy
CRSBuilder::optimize, so big part of Clusterify's code was reduced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156804 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Temporarily disable anti-dependence breaking for Mips until bug 12829 isAkira Hatanaka
resolved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156801 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Create a struct representing register units in TableGen.Jakob Stoklund Olesen
Besides the weight, we also want to store up to two root registers per unit. Most units will have a single root, the leaf register they represent. Units created for ad hoc aliasing get two roots: The two aliasing registers. The root registers can be used to compute the set of overlapping registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156792 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Remove extraneous ';'.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156791 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Add a command line option to skip the delay slot filler pass entirely for Mips.Akira Hatanaka
The purpose of this option is to silence error messages issued by machine verifier passes and enable them to run to the end. If this option is not provided, -verify-machineinstrs complains when it discovers there is a non-terminator instruction (an instruction that is in a delay slot) after the first terminator in a basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156790 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14[Support/YAMLParser] Use rtrim on plain scalars.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14[Support/COFF] Make the order of members in symbol match the standard.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156785 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Fix use of uninitialized variable.David Blaikie
Found by GCC's maybe-uninitialized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156780 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Don't access MO reference after invalidating operand list.Jakob Stoklund Olesen
This should unbreak llvm-x86_64-linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Fix PR12821.Jakob Stoklund Olesen
RAFast must add an <imp-def> operand when it is rewriting a sub-register def that isn't a read-modify-write. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156777 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Move the capture analysis from MemoryDependencyAnalysis to a more general placeChad Rosier
so that it can be reused in MemCpyOptimizer. This analysis is needed to remove an unnecessary memcpy when returning a struct into a local variable. rdar://11341081 PR12686 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156776 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Revert 156634 upon request until code improvement changes are made.Brendon Cahoon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156775 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Rename @llvm.debugger to @llvm.debugtrap.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Release notes for MIPS backend.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156772 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Remove a stale forward declaration.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156770 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Remove the expensive BitVector::operator~().Jakob Stoklund Olesen
Returning a temporary BitVector is very expensive. If you must, create the temporary explicitly: Use BitVector(A).flip() instead of ~A. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156768 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Remove BitVector binops.Jakob Stoklund Olesen
These operators were crazy slow, calling malloc to return a temporary result. At the same time, they look very innocent when used in code. If you need temporary BitVectors to compute your thing, create them explicitly, and use the inplace logical operators. This makes the high cost explicit in the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156767 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Consider ad hoc aliasing when building RegUnits.Jakob Stoklund Olesen
Register units can be used to compute if two registers overlap: A overlaps B iff units(A) intersects units(B). With this change, the above holds true even on targets that use ad hoc aliasing (currently only ARM). This means that register units can be used to implement regsOverlap() more efficiently, and the register allocator can use the concept to model interference. When there is no ad hoc aliasing, the register units correspond to the maximal cliques in the register overlap graph. This is optimal, no other register unit assignment can have fewer units. With ad hoc aliasing, weird things are possible, and we don't try too hard to compute the maximal cliques. The current approach is always correct, and it works very well (probably optimally) as long as the ad hoc aliasing doesn't have cliques larger than pairs. It seems unlikely that any target would need more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156763 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Record the ad hoc aliasing graph in CodeGenRegister.Jakob Stoklund Olesen
The ad hoc aliasing specified in the 'Aliases' list in .td files is currently only used by computeOverlaps(). It will soon be needed to build accurate register units as well, so build the undirected graph in CodeGenRegister::buildObjectGraph() instead. Aliasing is a symmetric relationship with only one direction specified in the .td files. Make sure both directions are represented in getExplicitAliases(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156762 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Compute topological signatures of registers.Jakob Stoklund Olesen
TableGen creates new register classes and sub-register indices based on the sub-register structure present in the register bank. So far, it has been doing that on a per-register basis, but that is not very efficient. This patch teaches TableGen to compute topological signatures for registers, and use that to reduce the amount of redundant computation. Registers get the same TopoSig if they have identical sub-register structure. TopoSigs are not currently exposed outside TableGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Add BitVector::anyCommon().Jakob Stoklund Olesen
The existing operation (A & B).any() is very slow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14SwitchInst cosmetics: renamed "Hash" method to "hash"Stepan Dyatkovskiy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156757 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Formatting changes. Remove the '...' placeholders.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156756 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Use ArrayRef instead of an explicit vector type.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-14Add blurb about Julia.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156754 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-13ReleaseNotes: Add info on PTX back-endJustin Holewinski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156745 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-13Hexagon: Initialize TBB to 0.Benjamin Kramer
Found by valgrind. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156744 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-13Fix Xcode case (Upper X, lower c)Jean-Daniel Dupas
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156743 91177308-0d34-0410-b5e6-96231b3b80d8
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