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2011-08-08ARM parsing and encoding for LDRB instruction.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Add FIXME.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137070 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM.Jakob Stoklund Olesen
They improve the verbose assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137069 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Add support for several vector shifts operations while in AVX mode. Fix PR10581Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137067 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08ARM load/store label parsing.Jim Grosbach
Allow labels for load/store instructions when parsing. There's encoding issues, still, so this doesn't work all the way through, yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Hoist hasLoadFromStackSlot and hasStoreToStackSlot.Jakob Stoklund Olesen
These the methods are target-independent since they simply scan the memory operands. They can live in TargetInstrInfoImpl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Fix encodings for Thumb ASR and LSR immediate operands. They encode the ↵Owen Anderson
range 1-32, with 32 encoded as 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are ↵Eli Friedman
correctly active without HasT2ExtractPack. PR10611. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137061 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Pacify virtual dtor warnings and cmake buildbots.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Add MCInstrAnalysis class. This allows the targets to specify own versions ↵Benjamin Kramer
of MCInstrDescs functions. - Add overrides for ARM. - Teach llvm-objdump to use this instead of plain MCInstrDesc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08llvm-objdump: disassembly enhancementsBenjamin Kramer
- Indent simple loops - Print unreachable blocks as .byte directives git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137058 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08llvm-objdump: Use help of CFG to print assembly when --cfg is passed.Benjamin Kramer
This way we can avoid printing unreachable code (data). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Simplify by creating parent first.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137056 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Don't clobber pending ST regs when FP regs are killed.Jakob Stoklund Olesen
X86FloatingPoint keeps track of pending ST registers for an upcoming inline asm instruction with fixed stack register constraints. It does this by remembering which FP register holds the value that should appear at a fixed stack position for the inline asm. When that FP register is killed before the inline asm, make sure to duplicate it to a scratch register, so the ST register still has a live FP reference. This could happen when the same FP register was copied to two ST registers, or when a spill instruction is inserted between the ST copy and the inline asm. This fixes PR10602. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137050 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Clean up the grammar for the landingpad instruction.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Remove unnecessary space.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137041 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Fix typo found by John.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-07strengthen up an assertion: you can't create a constant structChris Lattner
with an opaque struct type, it doesn't make sense. This should resolve PR10473. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-06Fix typo. Thanks, Andy!Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-06Made SCEV's UDiv expressions more canonical. When dividing aAndrew Trick
recurrence, the initial values low bits can sometimes be ignored. To take advantage of this, added FoldIVUser to IndVarSimplify to fold an IV operand into a udiv/lshr if the operator doesn't affect the result. -indvars -disable-iv-rewrite now transforms i = phi i4 i1 = i0 + 1 idx = i1 >> (2 or more) i4 = i + 4 into i = phi i4 idx = i0 >> ... i4 = i + 4 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Reject RS_Spill ranges from local splitting as well.Jakob Stoklund Olesen
All new local ranges are marked as RS_New now, so there is no need to attempt splitting of RS_Spill ranges any more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137002 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Only mark remainder intervals as RS_Spill after per-block splitting.Jakob Stoklund Olesen
The local ranges created get to stay in the RS_New stage, just like for local and region splitting. This gives tryLocalSplit a bit more freedom the first time it sees one of these new local ranges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Remember to update LiveDebugVariables after per-block splitting.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136996 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Extract per-block splitting into its own method.Jakob Stoklund Olesen
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136994 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Delete getMultiUseBlocks and splitSingleBlocks.Jakob Stoklund Olesen
These functions are no longer used, and they are easily replaced with a loop calling shouldSplitSingleBlock and splitSingleBlock. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136993 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Also use shouldSplitSingleBlock() in the fallback splitting mode.Jakob Stoklund Olesen
Drop the use of SplitAnalysis::getMultiUseBlocks, there is no need to go through a SmallPtrSet any more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136992 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Split around single instructions to enable register class inflation.Jakob Stoklund Olesen
Normally, we don't create a live range for a single instruction in a basic block, the spiller does that anyway. However, when splitting a live range that belongs to a proper register sub-class, inserting these extra COPY instructions completely remove the constraints from the remainder interval, and it may be allocated from the larger super-class. The spiller will mop up these small live ranges if we end up spilling anyway. It calls them snippets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136989 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05ARM load instruction shifted register index operands.Jim Grosbach
Parsing and encoding for shifted index operands for load instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05ARM indexed load assembly parsing and encoding.Jim Grosbach
More parsing support for indexed loads. Fix pre-indexed with writeback parsing for register offsets and handle basic post-indexed offsets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Detect proper register sub-classes.Jakob Stoklund Olesen
Some instructions require restricted register classes, but most of the time that doesn't affect register allocation. For example, some instructions don't work with the stack pointer, but that is a reserved register anyway. Sometimes it matters, GR32_ABCD only has 4 allocatable registers. For such a proper sub-class, the register allocator should try to enable register class inflation since that makes more registers available for allocation. Make sure only legal super-classes are considered. For example, tGPR is not a proper sub-class in Thumb mode, but in ARM mode it is. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05ARM refactor indexed store instructions.Jim Grosbach
Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136978 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Add ARM LDR parsing tests.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Fix liveness computations in BranchFolding.Jakob Stoklund Olesen
The old code would look at kills and defs in one pass over the instruction operands, causing problems with this code: %R0<def>, %CPSR<def,dead> = tLSLri %R5<kill>, 2, pred:14, pred:%noreg %R0<def>, %CPSR<def,dead> = tADDrr %R4<kill>, %R0<kill>, pred:14, %pred:%noreg The last instruction kills and redefines %R0, so it is still live after the instruction. This caused a register scavenger crash when compiling 483.xalancbmk for armv6. I am not including a test case because it requires too much bad luck to expose this old bug. First you need to convince the register allocator to use %R0 twice on the tADDrr instruction, then you have to convince BranchFolding to do something that causes it to run the register scavenger on he bad block. <rdar://problem/9898200> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136973 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05ARM simplify the postidx_reg operand encoding.Jim Grosbach
The immediate portion of the operand is just a boolean (the 'U' bit indicating add vs. subtract). Treat it as such. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05ARM use a dedicated printer for postidx_reg operands.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136968 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Add missing register constraint for some VLD3/VLD4 pseudo instructions.Bob Wilson
<rdar://problem/9878189> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136962 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Silence unused variable warnings in release builds.Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136956 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Fix http://llvm.org/bugs/show_bug.cgi?id=10583\n - test for 1 and 2 byte ↵Jason W Kim
fixups to be added git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-05Temporarily revert r135528 which distinguishes between two copies of oneChandler Carruth
inlined variable, based on the discussion in PR10542. This explodes the runtime of several passes down the pipeline due to a large number of "copies" remaining live across a large function. This only shows up with both debug and opt, but when it does it creates a many-minute compile when self-hosting LLVM+Clang. There are several other cases that show these types of regressions. All of this is tracked in PR10542, and progress is being made on fixing the issue. Once its addressed, the re-instated, but until then this restores the performance for self-hosting and other opt+debug builds. Devang, let me know if this causes any trouble, or impedes fixing it in any way, and thanks for working on this! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Fix broken encodings for the Thumb2 LDRD/STRD instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136942 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04ARM assembly parsing and encoding for LDR instructions.Jim Grosbach
Enhance support for LDR instruction assembly parsing for post-indexed addressing with immediate values. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Count the total amount of stack space used in compiled functions.Jakob Stoklund Olesen
Patch by Ivan Krasin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Print DBG_VALUE variable's location info as a comment.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136916 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Increment counter inside insertDebugValue().Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136915 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04We need to map DebugLoc. It leads to Fuction * (through subprogram entry ↵Devang Patel
node) which should be appropriately mapped. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136910 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Linke NamedMDNodes after linking global values as comment suggests.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136909 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04allow \r's in .s files.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136908 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Introduce adjustFixupOffset that adjusts the fixup offset of a relocation.Roman Divacky
This is meant to be overriden by backends. Implement an override on PowerPC which adjusts the offset by 2 for ha16/lo16 relocation kinds. This removes a commented out hack and enables hello world to be compiled on PowerPC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Add counter.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136901 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Fix an obvious type. Patch by Ivan Krasin.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136900 91177308-0d34-0410-b5e6-96231b3b80d8
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