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2011-09-03Enforce subtarget checks in a few places to be explicit when theBruno Cardoso Lopes
pattern should be matched git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03Tidy up code moving patterns to their appropriate place!Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to useBruno Cardoso Lopes
it! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03Teach X86FastISel to use AVX versions of instructions when possibleBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03Fix 80-column and styleBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139061 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03Tidy up some SSE/AVX convert intrinsics. Also add an AVX version ofBruno Cardoso Lopes
OptForSize pattern git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03Fix a truly heinous bug in DAGCombine related to AssertZext.Owen Anderson
If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert. The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users. No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem. Fixes <rdar://problem/10063365>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-03Revert r129875, XFAILing this test for arm, since the fix was reverted.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139058 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Pseudo CMOV instructions don't clobber EFLAGS.Jakob Stoklund Olesen
The explanation about a 0 argument being materialized as xor is no longer valid. Rematerialization will check if EFLAGS is live before clobbering it. The code produced by X86TargetLowering::EmitLoweredSelect does not clobber EFLAGS. This causes one less testb instruction to be generated in the cmov.ll test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Check for EFLAGS live-out before clobbering it.Jakob Stoklund Olesen
It is only allowed to clobber EFLAGS at the end of a block if it isn't live-in to any successor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139056 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Use existing function.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139055 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Thumb2 parsing and encoding for CBZ/CBNZ.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139054 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Thumb2 parsing and encoding for BXJ.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139053 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Thumb2 parsing and encoding for BIC.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139052 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Thumb2 parsing and encoding for BFI.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139051 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Thumb2 parsing and encoding for BFC.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139050 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Thumb2 parsing and encoding of B instruction.Jim Grosbach
Tweak handling of IT blocks a bit to enable this. The differentiation between B and Bcc needs special sauce. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Attempt to silence known valgrind errors.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139048 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Remove unused variables.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Try to eliminate the use of the 'unwind' instruction.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Don't fast-isel for atomic load/store; some cases require extra handling ↵Eli Friedman
missing from fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Thumb2 parsing and encoding for ASR.Jim Grosbach
For other shift and rotate instructions, too. Tests for those forthcoming as I work my way through the ISA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139040 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Better fix for this testcase. Update it to the new EH scheme entirely.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Update for new EH stuff. (I'm not sure if this is 100% correct.)Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Test case update for unroll-scev.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139037 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Comment and clarifying assert.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139036 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02No need to get fancy inserting a PHI node when the values are stored in stackBill Wendling
slots. This fixes a bug where the number of nodes coming into the PHI node may not equal the number of predecessors. E.g., two or more landingpad instructions may require a PHI before reaching the eh.exception and eh.selector instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139035 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Make RecordVal Name an InitDavid Greene
Store a RecordVal's name as an Init to allow class-qualified Record members to reference Records that have Init names. We'll use this to provide more programmability in how we name defs and their associated members. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139031 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Change X86 disassembly to print immediates values as signed by default. SpecialKevin Enderby
case those instructions that the immediate is not sign-extend. radr://8795217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Tidy up. Formatting.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Update comments to reflect reality.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Tidy up. 80 columns.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Thumb2 parsing and encoding for AND (register).Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Simplify by using isFullCopy().Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139019 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Revert r138826 until PR10834 can be fixed.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Thumb2 parsing and encoding for ADD (register).Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Darwin wants ctors/dtors to be ordered the other way round to linux.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.Kevin Enderby
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139014 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Tests for Thumb2 AND (immediate) instruction.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Extra CHECK-NOT to make sure that GVN transform works properly.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139012 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02-unroll-scev flag removalAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139010 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Enable SCEV-based unrolling by default.Andrew Trick
This changes loop unrolling to use the same mechanism for trip count computation as indvars. This is a stronger check that tends to unroll more loops. A very common side-effect is that many single iteration loops will be removed sooner. The real goal was simply to remove dependence on canonical IVs. x86 is break even. ARM performance changes to expect (+ is good): External/SPEC/CFP2000/183.equake/183.equake +13% SingleSource/Benchmarks/Dhrystone/fldry +21% MultiSource/Applications/spiff/spiff +3% SingleSource/Benchmarks/Stanford/Puzzle -14% The Puzzle regression is actually an improvement in loop optimization that defeats GVN: rdar://problem/10065079. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139009 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Add FIXME. Thumb2 ADR encoding choice is non-trivial.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Return undef value (instead of arbitrary) for wrong or undef index inJakub Staszak
ConstantVector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02ConstantVector returns arbitrary value for the wrong index.Jakub Staszak
This fixes PR10813. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139006 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Compare type size instead of type _store_ size to make sure that BitCastInstJakub Staszak
will be valid. This fixes PR10820. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.Kalle Raiskila
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form ↵Craig Topper
from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Perform the upgrading of the old EH to the new EH in a more sane manner.Bill Wendling
Perform the upgrading in steps. * First, create a map of the invokes to the EH intrinsics. * Next, take that mapping and determine if the invoke's unwind destination has a single predecessor. If not, then create a new empty block to hold the new landingpad instruction. * Create a landingpad instruction into the uwnind destination. Fill it with the values from the old selector. Map the old intrinsic calls to the new landingpad values (there may be multiple landingpad instructions per instrinic call pairs). * Go through the old intrinsic calls, create a PHI node when necessary, and then replace their values with the new values from the landingpad instructions. * Delete all dead instructions. * ??? * Profit! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02Update to new EH scheme.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138989 91177308-0d34-0410-b5e6-96231b3b80d8
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