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2012-08-28Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162738 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28llvm/test/CodeGen/X86/pr12312.ll: Add -mtriple=x86_64-unknown-unknown.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162736 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Fix PR12312Michael Liao
- Add a target-specific DAG optimization to recognize a pattern PTEST-able. Such a pattern is a OR'd tree with X86ISD::OR as the root node. When X86ISD::OR node has only its flag result being used as a boolean value and all its leaves are extracted from the same vector, it could be folded into an X86ISD::PTEST node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162735 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Check all patterns for missing instruction flags.Jakob Stoklund Olesen
Both single-instruction and multi-instruction patterns can be checked for missing mayLoad / mayStore, and hasSideEffects flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162734 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Remove extra MayLoad/MayStore flags from atomic_load/store.Jakob Stoklund Olesen
These extra flags are not required to properly order the atomic load/store instructions. SelectionDAGBuilder chains atomics as if they were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on the memory operands of all atomic operations. The volatile bit is enough to order atomic loads and stores during and after SelectionDAG. This means we set mayLoad on atomic_load, mayStore on atomic_store, and mayLoad+mayStore on the remaining atomic read-modify-write operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ↵Jakob Stoklund Olesen
ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162732 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Fix mips' long branch pass.Akira Hatanaka
Instructions emitted to compute branch offsets now use immediate operands instead of symbolic labels. This change was needed because there were problems when R_MIPS_HI16/LO16 relocations were used to make shared objects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162731 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Split several PPC instruction classes.Hal Finkel
Slight reorganisation of PPC instruction classes for scheduling. No functionality change for existing subtargets. - Clearly separate load/store-with-update instructions from regular loads and stores. - Split IntRotateD -> IntRotateD and IntRotateDI - Split out fsub and fadd from FPGeneral -> FPAddSub - Update existing itineraries Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162729 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Fix bug 13532.Akira Hatanaka
In SelectionDAGLegalize::ExpandLegalINT_TO_FP, expand INT_TO_FP nodes without using any f64 operations if f64 is not a legal type. Patch by Stefan Kristiansson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Allow remat of LI on PPC.Hal Finkel
Allow load-immediates to be rematerialised in the register coalescer for PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail, because it relies on a register move getting emitted. The immediate load is equivalent, so change this test case. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162727 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Add the Freescale vendor to Triple.Hal Finkel
Adds the vendor 'fsl' (used by Freescale SDK) to Triple. This will allow clang support for Freescale cross-compile configurations. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Eliminate redundant CR moves on PPC32.Hal Finkel
The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and unset if it doesn't. The solution up to now was to insert a MachineNode to set/unset the CR bit, which produces a CR vreg. This vreg was then copied into CR bit 6. When the register allocator saw a bunch of these in the same function, it allocated the set/unset CR bit in some random CR register (1 extra instruction) and then emitted CR moves before every vararg function call, rather than just setting and unsetting CR bit 6 directly before every vararg function call. This patch instead inserts a PPCcrset/PPCcrunset instruction which are then matched by a dedicated instruction pattern. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Optimize zext on PPC64.Hal Finkel
The zeroextend IR instruction is lowered to an 'and' node with an immediate mask operand, which in turn gets legalised to a sequence of ori's & ands. This can be done more efficiently using the rldicl instruction. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28Temporarily revert this to bring back the bots.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162722 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28More missing mayLoad flags on AVX multiclasses.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162714 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.Jakob Stoklund Olesen
It is not safe to use normal LDR instructions because they may be reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag that prevents reordering. Atomic loads are also prevented from participating in rematerialization and load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162713 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Add --program-prefix support to build.Sebastian Pop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162707 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Fix compile error when building with C++11 - clang thinks that PRIx64 is a ↵Marshall Clow
user-defined suffix or something git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Make sure we add the predicate after all of the registers are added.Bill Wendling
<rdar://problem/12183003> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162703 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Don't use for loops for code that is only intended to execute once. NoDan Gohman
intended functionality change. Thanks to Ahmed Charles for spotting it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162686 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Fix comment.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162678 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Fix comment for function RuntimeDyldImpl.resolveRelocation()Danil Malyshev
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162677 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Remove the the block_node_iterator of Region, replace it by the block_iterator.Hongbin Zheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162672 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Support MIPS DSP Rev2 intrinsics.Simon Atanasyan
The patch reviewed by Akira Hatanaka. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162668 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27llvm/test/CodeGen/X86/fma.ll: Add -march=x86, or two tests would fail on ↵NAKAMURA Takumi
non-x86 hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162667 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27DWARFDebugRangeList.cpp: Use PRIx64 for uint64_t as format string.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27llvm/test/CodeGen/X86/fma_patterns.ll: Add -mtriple=x86_64. It was ↵NAKAMURA Takumi
incompatible on i686 and Windows x64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Remove MMX shift intrinsic handling code that also exists in ↵Craig Topper
SelectionDAGBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162661 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Commit test change for r162658.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162660 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27[DebugInfo] fixup for r162657: update CMakeLists.txtAlexey Samsonov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Don't allow vextractf128 to be folded with unaligned stores. We don't fold ↵Craig Topper
unaligned loads so shouldn't fold unaligned stores as it can cause an alignment fault to occur. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162658 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Add basic support for .debug_ranges section to LLVM's DebugInfo library.Alexey Samsonov
This section (introduced in DWARF-3) is used to define instruction address ranges for functions that are not contiguous and can't be described by low_pc/high_pc attributes (this is the usual case for inlined subroutines). The patch is the first step to support fetching complete inlining info from DWARF. Reviewed by Benjamin Kramer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Fold some patterns into instruction definitons so tablegen can infer flags ↵Craig Topper
removing the need for an explicit 'neverHasSideEffects = 1' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162656 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27FMA3 tests on bdver2 target for changes made in rev 162012. Also madeAnitha Boyapati
corresponding changes to existing tests for darwin triple to ensure that same pattern is tested for bdver2 target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Add HasAVX1Only predicate and use it for patterns that have an AVX1 ↵Craig Topper
instruction and an AVX2 instruction rather than relying on AddedComplexity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Make sure that FMA3 is favored even when FMA4 is also enabled. Test case for ↵Craig Topper
r162454. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162653 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-27Pass -lLTO after gold-plugin.o so that it gets used in systems that default toRafael Espindola
--as-needed. Patch by Felix Geyer. Fixes pr13262. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162652 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-26Mark avx2 maskstore has ReadWriteArgMem. Mark broadcast and maskload as ↵Craig Topper
ReadArgMem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith
Reviewed offline by chandlerc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Add missing mayLoad flags to a large class of AVX *_Int instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Missed tLEApcrelJT.Jakob Stoklund Olesen
ARMConstantIslandPass expects this instruction to stay in the same basic block as the jump table branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162615 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Infer instruction properties from single-instruction patterns.Jakob Stoklund Olesen
Previously, instructions without a primary patterns wouldn't get their properties inferred. Now, we use all single-instruction patterns for inference, including 'def : Pat<>' instances. This causes a lot of instruction flags to change. - Many instructions no longer have the UnmodeledSideEffects flag because their flags are now inferred from a pattern. - Instructions with intrinsics will get a mayStore flag if they already have UnmodeledSideEffects and a mayLoad flag if they already have mayStore. This is because intrinsics properties are linear. - Instructions with atomic_load patterns get a mayStore flag because atomic loads can't be reordered. The correct workaround is to create pseudo-instructions instead of using normal loads. PR13693. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162614 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Explicitly mark LEApcrel pseudos with hasSideEffects.Jakob Stoklund Olesen
It's not clear that they should be marked as such, but tbb formation fails if t2LEApcrelJT is hoisted of of a loop. This doesn't change the flags on these instructions, UnmodeledSideEffects was already inferred from the missing pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Stop inferring isVariadic from instruction patterns.Jakob Stoklund Olesen
Instructions are now only marked as variadic if they use variable_ops in their ins list. A variadic SDNode is typically used for call nodes that have the call arguments as operands. A variadic MachineInstr can actually encode a variable number of operands, for example ARM's stm/ldm instructions. A call instruction does not have to be variadic. The call argument registers are added as implicit operands. This change remove the MCID::Variadic flags from most call and return instructions, allowing us to better verify their operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Fix call instruction operands in ARMFastISel.Jakob Stoklund Olesen
The ARM BL and BLX instructions don't have predicate operands, but the thumb variants tBL and tBLX do. The argument registers should be added as implicit uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Mark X86::RET and RETI instructions as variadic.Jakob Stoklund Olesen
There is special magic happening when returning floating point values on the x87 stack. The RET instructions get extra f80 operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162592 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Avoid including explicit uses when counting SDNode imp-uses.Jakob Stoklund Olesen
It is legal to have a register node as an explicit operand, it shouldn't be counted as an implicit use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Disable Mips' delay slot filler when optimization level is O0.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162589 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if itsAkira Hatanaka
second operand is MipsISD::GPRel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162584 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24Forgot to check in ProfileDataTypes.h in r162576Manman Ren
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162578 91177308-0d34-0410-b5e6-96231b3b80d8
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