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2013-03-20Make sure TableGen exits with an error code after printing errors.Jakob Stoklund Olesen
This makes it possible to report multiple errors in one invocation. There are already calls to PrintError in CodeGenDAGPatterns.cpp which previously would not cause TableGen to fail. <rdar://problem/13463339> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177573 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Refactor file/directory path in namespace debug info to refer directly to ↵David Blaikie
the pair rather than the DIFile (paired to a Clang test - excuse the buildbot skew/fallout) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177566 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Enhance debug info namespace test to check for context/scope referenceDavid Blaikie
The differing file (due to the #line directive in the original source) is for future testing improvements coming soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177560 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Remove blank line before block comment.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177550 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20DIBuilder: allow linkage name to be specified for global variablesDavid Blaikie
Patch by Kai Nacke (kai@redstar.de) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177547 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Make target-specific test case in r177474 only run when that target is builtDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177545 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Add timing of the IR parsing code with a new -time-ir-parsing flagEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177543 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Add some missing SSE annotations.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177540 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Annotate remaining IIC_BIN_* instructions.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177539 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Revert "pre-RA-sched: fix TargetOpcode usage"Christian Konig
This reverts commit 06091513c283c863296f01cc7c2e86b56bb50d02. The code is obviously wrong, but the trivial fix causes inefficient code generation on X86. Somebody with more knowledge of the code needs to take a look here. Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177529 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Move SDNode order propagation to SDNodeOrdering, which also fixes a missedJustin Holewinski
case of order propagation during isel. Thanks Owen for the suggestion! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20pre-RA-sched: fix TargetOpcode usageChristian Konig
TargetOpcodes need to be treaded as Machine- and not ISD-Opcodes. Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177518 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Fix a silly search-and-replace goof with r177495 that only brokeChandler Carruth
non-release builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177498 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20[SROA] Don't preserve the IR names in release builds.Chandler Carruth
This is espcially important because the new SROA pass goes to great lengths to provide helpful names for debugging, and as a consequence they can become very slow to render. Good for between 5% and 15% of the SROA runtime on some slow test cases such as the one in PR15412. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177495 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Move the endif to the correct line so we don't have warnings aboutChandler Carruth
unused statistics variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177494 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Introduce some new statistics to help track the exact behavior of theChandler Carruth
new SROA pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177493 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Reorder the DIFile parameter in DINameSpaceDavid Blaikie
Moving the DIFile parameter to immediately proceed the tag so that it will be a common prefix with other DIScopes (once the DIFile is replaced with the raw file/directory pair). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177492 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Add a test case for PR15318 fixed in r177472Hao Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177489 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Don't assume the test directory is writable, use %T to find a writableNick Lewycky
directory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177488 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Test DW_TAG_namespace support in the backendDavid Blaikie
This is the backend portion of a Clang test case (clang/test/CodeGenCXX/debug-info-namespace.cpp) that was roughly/coarsely testing LLVM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177487 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Provide more details for DINameSpace debug info in the IR comment annotationsDavid Blaikie
Sorry for the version skew - I should've committed this before the corresponding Clang test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177486 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Fix PR15296Michael Liao
- Move SRA/SRL/SHL lowering support from DAG combination to DAG lowering to support extended 256-bit integer in AVX but not AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177478 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Mark all variable shifts needing customizingMichael Liao
- Prepare moving logic from DAG combining into DAG lowering. There's no functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177477 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Move scalar immediate shift lowering into a dedicated funcMichael Liao
- no functionality change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Fix test case regression on ARM & PPC introduced r177239David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177474 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Fix AsmPrinter crashes with assertion. Bug 15318 in BugzillaHao Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177472 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Refactor the DIFile (2nd) parameter to DITypes to be an MDNode reference to ↵David Blaikie
a raw directory/file pair This makes DIType's first non-tag parameter the same as DIFile's, allowing them to both share the common implementation of getFilename/getDirectory in DIScope. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177467 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-20Propagate DAG node ordering during type legalization and instruction selectionJustin Holewinski
A node's ordering is only propagated during legalization if (a) the new node does not have an ordering (is not a CSE'd node), or (b) the new node has an ordering that is higher than the node being legalized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177465 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Fix pr13145 - Naming a function like a register name confuses the asm parser.Chad Rosier
Patch by Stepan Dyatkovskiy <stpworld@narod.ru> rdar://13457826 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177463 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Move the DIFile operand to DITypes from the 4th operand to the 2nd.David Blaikie
This is another step along the way to making all DIScopes have a common prefix which can be added to in a general manner to support using directives (DW_TAG_imported_module). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177462 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Annotate various null idioms with SchedRW lists.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177461 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Annotate SSE float conversions with SchedRW lists.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177460 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Annotate X86InstrCMovSetCC.td with SchedRW lists.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Formatting fixups.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177458 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Dead code.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177451 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Dead code.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177450 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19[ms-inline asm] Move the immediate asm rewrite into the target specificChad Rosier
logic as a QOI cleanup. No functional change. Tests already in place. rdar://13456414 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Update global merge pass according to Duncan's advices:Quentin Colombet
- Remove useless includes - Change misleading comments - Move code into doFinalization git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177445 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Annotate X86InstrCompiler.td with SchedRW lists.Jakob Stoklund Olesen
Add a new WriteZero SchedWrite type for the common dependency-breaking instructions that clear a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177442 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19[ms-inline asm] Remove the brackets from X86Operand in the IR. These will beChad Rosier
added back in by X86AsmPrinter::printIntelMemReference() during codegen. Previously, this following example void t() { int i; __asm mov eax, [i] } would generate the below assembly mov eax, dword ptr [[eax]] which resulted in a fatal error when compiling. Test case coming on the clang side. rdar://13444264 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177440 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19[ms-inline asm] Create a helper function, CreateMemForInlineAsm, that createsChad Rosier
an X86Operand, but also performs a Sema lookup and adds the sizing directive when appropriate. Use this when parsing a bracketed statement. This is necessary to get the instruction matching correct as well. Test case coming on clang side. rdar://13455408 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177439 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Register the GCOV writeout functions so that they're emitted serially.Bill Wendling
We don't want to write out >1000 files at the same time. That could make things prohibitively expensive. Instead, register the "writeout" function so that it's emitted serially. <rdar://problem/12439551> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177437 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Add a comment to the CodeGen/PowerPC/asym-regclass-copy.ll testHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177434 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19IndVarSimplify: do not recompute an IV value outside of the loop if :Arnaud A. de Grandmaison
- it is trivially known to be used inside the loop in a way that can not be optimized away - there is no use outside of the loop which can take advantage of the computation hoisting git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177432 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Add missing mayLoad flag to LHAUX8 and LWAUX.Ulrich Weigand
All pre-increment load patterns need to set the mayLoad flag (since they don't provide a DAG pattern). This was missing for LHAUX8 and LWAUX, which is added by this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177431 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Rewrite LHAU8 pattern to use standard memory operand.Ulrich Weigand
As opposed to to pre-increment store patterns, the pre-increment load patterns were already using standard memory operands, with the sole exception of LHAU8. As there's no real reason why LHAU8 should be different here, this patch simply rewrites the pattern to also use a memri operand, just like all the other patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177430 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Rewrite pre-increment store patterns to use standard memory operands.Ulrich Weigand
Currently, pre-increment store patterns are written to use two separate operands to represent address base and displacement: stwu $rS, $ptroff($ptrreg) This causes problems when implementing the assembler parser, so this commit changes the patterns to use standard (complex) memory operands like in all other memory access instruction patterns: stwu $rS, $dst To still match those instructions against the appropriate pre_store SelectionDAG nodes, the patch uses the new feature that allows a Pat to match multiple DAG operands against a single (complex) instruction operand. Approved by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177429 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Extend TableGen instruction selection matcher to improve handlingUlrich Weigand
of complex instruction operands (e.g. address modes). Currently, if a Pat pattern creates an instruction that has a complex operand (i.e. one that consists of multiple sub-operands at the MI level), this operand must match a ComplexPattern DAG pattern with the correct number of output operands. This commit extends TableGen to alternatively allow match a complex operands against multiple separate operands at the DAG level. This allows using Pat patterns to match pre-increment nodes like pre_store (which must have separate operands at the DAG level) onto an instruction pattern that uses a multi-operand memory operand, like the following example on PowerPC (will be committed as a follow-on patch): def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst), "stwu $rS, $dst", LdStStoreUpd, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff), (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>; Here, the pair of "ptroff" and "ptrreg" operands is matched onto the complex operand "dst" of class "memri" in the "STWU" instruction. Approved by Jakob Stoklund Olesen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177428 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Fix sub-operand size mismatch in tocentry operands.Ulrich Weigand
The tocentry operand class refers to 64-bit values (it is only used in 64-bit, where iPTR is a 64-bit type), but its sole suboperand is designated as 32-bit type. This causes a mismatch to be detected at compile-time with the TableGen patch I'll check in shortly. To fix this, this commit changes the suboperand to a 64-bit type as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177427 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-19Remove an invalid and unnecessary Pat pattern from the X86 backend:Ulrich Weigand
def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))), (MOV64rm tglobaltlsaddr :$dst)>; This pattern is invalid because the MOV64rm instruction expects a source operand of type "i64mem", which is a subclass of X86MemOperand and thus actually consists of five MI operands, but the Pat provides only a single MI operand ("tglobaltlsaddr" matches an SDnode of type ISD::TargetGlobalTLSAddress and provides a single output). Thus, if the pattern were ever matched, subsequent uses of the MOV64rm instruction pattern would access uninitialized memory. In addition, with the TableGen patch I'm about to check in, this would actually be reported as a build-time error. Fortunately, the pattern does in fact never match, for at least two independent reasons. First, the code generator actually never generates a pattern of the form (load (X86Wrapper (tglobaltlsaddr))). For most combinations of TLS and code models, (tglobaltlsaddr) represents just an offset that needs to be added to some base register, so it is never directly dereferenced. The only exception is the initial-exec model, where (tglobaltlsaddr) refers to the (pc-relative) address of a GOT slot, which *is* in fact directly dereferenced: but in that case, the X86WrapperRIP node is used, not X86Wrapper, so the Pat doesn't match. Second, even if some patterns along those lines *were* ever generated, we should not need an extra Pat pattern to match it. Instead, the original MOV64rm instruction pattern ought to match directly, since it uses an "addr" operand, which is implemented via the SelectAddr C++ routine; this routine is supposed to accept the full range of input DAGs that may be implemented by a single mov instruction, including those cases involving ISD::TargetGlobalTLSAddress (and actually does so e.g. in the initial-exec case as above). To avoid build breaks (due to the above-mentioned error) after the TableGen patch is checked in, I'm removing this Pat here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177426 91177308-0d34-0410-b5e6-96231b3b80d8
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