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2013-03-15Add a triple to the test.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177131 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Unaligned loads should use the VMOVUPS opcode.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Remove some unused variables to clean the Clang -Werror buildDavid Blaikie
(these were added in r177089) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177129 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[mips] Set isAllocatable bit of unallocatable register classes to 0.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177128 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Fix r177112: Add ProcResGroup.Andrew Trick
This is the other half of r177122 that I meant to commit at the same time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Prepare for adding InstrSchedModel annotations to X86 instructions.Jakob Stoklund Olesen
The new InstrSchedModel is easier to use than the instruction itineraries. It will be used to model instruction latency and throughput in modern Intel microarchitectures like Sandy Bridge. InstrSchedModel should be able to coexist with instruction itinerary classes, but for cleanliness we should switch the Atom processor model to the new InstrSchedModel as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177122 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Add a new method which enables one to change register classes.Reed Kotler
See the Mips16ISetLowering.cpp patch to see a use of this. For now now the extra code in Mips16ISetLowering.cpp is a nop but is used for test purposes. Mips32 registers are setup and then removed and then the Mips16 registers are setup. Normally you need to add register classes and then call computeRegisterProperties. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14LoopVectorizer: Insert some white space to make test case more readableArnold Schwaighofer
Also remove some unneeded function attributes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177114 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[fast-isel] The X86FastISel::FastLowerArguments function doesn't properly handleChad Rosier
the win64 calling convention. rdar://13423768 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177113 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14MachineModel: Add a ProcResGroup class.Andrew Trick
This allows abitrary groups of processor resources. Using something in a subset automatically counts againts the superset. Currently, this only works if the superset is also a ProcResGroup as opposed to a SuperUnit. This allows SandyBridge to be expressed naturally, which will be checked in shortly. def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; def SBPort23 : ProcResGroup<[SBPort2, SBPort3]>; def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177112 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Move estimateStackSize from ARM into MachineFrameInfoHal Finkel
This is a generic function (derived from PEI); moving it into MachineFrameInfo eliminates a current redundancy between the ARM and AArch64 backends, and will allow it to be used by the PowerPC target code. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Provide the register scavenger to processFunctionBeforeFrameFinalizedHal Finkel
Add the current PEI register scavenger as a parameter to the processFunctionBeforeFrameFinalized callback. This change is necessary in order to allow the PowerPC target code to set the register scavenger frame index after the save-area offset adjustments performed by processFunctionBeforeFrameFinalized. Only after these adjustments have been made is it possible to estimate the size of the stack frame. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177108 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Use frame-index scavenging for PPC register spillingHal Finkel
Make requiresFrameIndexScavenging return true, and create virtual registers in the spilling code instead of using the register scavenger directly. This makes the target-level code simpler, and importantly, delays the scavenging until after callee-saved register processing (which will be important for later changes). Also cleans up trackLivenessAfterRegAlloc (makes it inline in the header with the other related functions). This makes it clear that it always returns true. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Not all PPC functions with a frame pointer need a RS spill slotHal Finkel
We used to add a spill slot for the register scavenger whenever the function has a frame pointer. This is unnecessarily conservative: We may need the spill slot for dynamic stack allocations, and functions with dynamic stack allocations always have a FP, but we might also have a FP for other reasons (such as the user explicitly disabling frame-pointer elimination), and we don't necessarily need a spill slot for those functions. The structsinregs test needed adjustment because it disables FP elimination. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177106 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14ARM cost model: Increase cost of some vector selects we do terrible onArnold Schwaighofer
By terrible I mean we store/load from the stack. This matters on PAQp8 in _Z5trainPsS_ii (which is inlined into Mixer::update) where we decide to vectorize a loop with a VF of 8 resulting in a 25% degradation on a cortex-a8. LV: Found an estimated cost of 2 for VF 8 For instruction: icmp slt i32 LV: Found an estimated cost of 2 for VF 8 For instruction: select i1, i32, i32 The bug that tracks the CodeGen part is PR14868. radar://13403975 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[mips] Fix filename in comment and delete unnecessary lines of code.Akira Hatanaka
No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177104 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Hexagon: Removed asserts regarding alignment and offset.Jyotsna Verma
We are warning the user about the alignment, so we should not assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177103 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Add missing asserts flag to test - it uses debug flagsArnold Schwaighofer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Android uses cacheflush(long start, long end, long flags) for MIPS.Akira Hatanaka
Patch by Stephen Hines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177101 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14LoopVectorize: Invert case when we use a vector cmp value to query select costArnold Schwaighofer
We generate a select with a vectorized condition argument when the condition is NOT loop invariant. Not the other way around. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177098 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Add back lines which were accidentally deleted in CMakeLists.txt.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[mips] Define function MipsSEDAGToDAGISel::selectAddESubE.Akira Hatanaka
No intended functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177095 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Add a comment about overlapping PPC frame offsetsHal Finkel
I don't think that it is otherwise clear how the overlapping offsets are processed into distinct spill slots. Comment that this is done in processFunctionBeforeFrameFinalized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[mips] Rename functions and variables to start with proper case.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177092 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Add header file MipsISelDAGToDAG.h.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177090 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[mips] Define two subclasses of MipsDAGToDAGISel. Mips16DAGToDAGISel is forAkira Hatanaka
mips16 and MipsSEDAGToDAGISel is for mips32/64. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177089 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Perform factorization as a last resort of unsafe fadd/fsub simplification.Shuxin Yang
Rules include: 1)1 x*y +/- x*z => x*(y +/- z) (the order of operands dosen't matter) 2) y/x +/- z/x => (y +/- z)/x The transformation is disabled if the new add/sub expr "y +/- z" is a denormal/naz/inifinity. rdar://12911472 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177088 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Test that we emit a DW_AT_location for self captured by a block.Adrian Prantl
This is the backend part of a CFE test with the same name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177087 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14R600: Factorize code handling Const Read Port limitationVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[ASan] emit instrumentation for initialization order checking by defaultAlexey Samsonov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177063 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14PR14972: SROA vs. GVN exposed a really bad bug in SROA.Chandler Carruth
The fundamental problem is that SROA didn't allow for overly wide loads where the bits past the end of the alloca were masked away and the load was sufficiently aligned to ensure there is no risk of page fault, or other trapping behavior. With such widened loads, SROA would delete the load entirely rather than clamping it to the size of the alloca in order to allow mem2reg to fire. This was exposed by a test case that neatly arranged for GVN to run first, widening certain loads, followed by an inline step, and then SROA which miscompiles the code. However, I see no reason why this hasn't been plaguing us in other contexts. It seems deeply broken. Diagnosing all of the above took all of 10 minutes of debugging. The really annoying aspect is that fixing this completely breaks the pass. ;] There was an implicit reliance on the fact that no loads or stores extended past the alloca once we decided to rewrite them in the final stage of SROA. This was used to encode information about whether the loads and stores had been split across multiple partitions of the original alloca. That required threading explicit tracking of whether a *use* of a partition is split across multiple partitions. Once that was done, another problem arose: we allowed splitting of integer loads and stores iff they were loads and stores to the entire alloca. This is a really arbitrary limitation, and splitting at least some integer loads and stores is crucial to maximize promotion opportunities. My first attempt was to start removing the restriction entirely, but currently that does Very Bad Things by causing *many* common alloca patterns to be fully decomposed into i8 operations and lots of or-ing together to produce larger integers on demand. The code bloat is terrifying. That is still the right end-goal, but substantial work must be done to either merge partitions or ensure that small i8 values are eagerly merged in some other pass. Sadly, figuring all this out took essentially all the time and effort here. So the end result is that we allow splitting only when the load or store at least covers the alloca. That ensures widened loads and stores don't hurt SROA, and that we don't rampantly decompose operations more than we have previously. All of this was already fairly well tested, and so I've just updated the tests to cover the wide load behavior. I can add a test that crafts the pass ordering magic which caused the original PR, but that seems really brittle and to provide little benefit. The fundamental problem is that widened loads should Just Work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177055 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Updating branches/google/testing to r176857Alexander Kornienko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/google/testing@177020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Add two of the float related ARM-specific entries for e_flags needed forJoerg Sonnenberger
linkers to interact with GNU ld. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177016 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Fix the name of a variable to match its declaration. Fixes build failure ↵Craig Topper
from r177014. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177015 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit ↵Craig Topper
set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177014 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Teach X86 MC instruction lowering that VMOVAPSrr and other VEX-encoded ↵Craig Topper
register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177011 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Fix PR15309Michael Liao
- Fix the typo on type checking git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177010 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14test commit: remove blank line.Jiong Wang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177009 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Remove a change to the debug info in this test, that I made while testingNick Lewycky
something else and forgot to remove. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Try using %S to find the emitted .gcno file.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Remove accidentally committed debug line.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177005 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Refactor GCOV's six constructor arguments into a struct with a getter thatNick Lewycky
constructs default arguments. It can now take default arguments from cl::opt'ions. Add a new -default-gcov-version=... option, and actually test it! Sink the reverse-order of the version into GCOVProfiling, hiding it from our users. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177002 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14Fix typo in comment.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176997 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[Support][Test] Missed this in the API change.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176996 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14[Support] Fix lifetime of file descriptors when using MemoryBuffer.Michael J. Spencer
Clients of MemoryBuffer::getOpenFile expect it not to take ownership of the file descriptor passed in. So don't. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176995 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13No functionality change. Rename emitGCNO() to the more sensibleNick Lewycky
emitProfileNotes(), similar to emitProfileArcs(). Also update its comment. Also add a comment on Version[4] (there will be another comment in clang later), and compress lines that exceeded 80 columns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176994 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13Simplify file/directory name handling in DILexicalBlockDavid Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176993 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13Remove an extra operand to a DIFile metadata entryDavid Blaikie
(extra cleanup/fallout from r176983 - not sure why I didn't catch this locally) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176988 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13Reset some of the target options which affect code generation.Bill Wendling
This doesn't reset all of the target options within the TargetOptions object. This is because some of those are ABI-specific and must be determined if it's okay to change those on the fly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-13Simplify directory name handling in DILexicalBlockFile.David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176984 91177308-0d34-0410-b5e6-96231b3b80d8
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