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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122243 91177308-0d34-0410-b5e6-96231b3b80d8
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mayBeOverridden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122241 91177308-0d34-0410-b5e6-96231b3b80d8
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revision id is appended to the LLVM version string. Defaults to
OFF.
Until now the VC revision id was always appended to the revision
string whenever cmake was invoked (either explicitly or implicitly
because a cmake source file changed). This was causing massive
recompilations because config.h are reconfigured with the new contents
of PACKAGE_VERSION.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122240 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122239 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122238 91177308-0d34-0410-b5e6-96231b3b80d8
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to make sure that the reused alloca has sufficient alignment.
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argument. The generated alloca has to have at least the alignment of the
byval, if not, the client may be making assumptions that the new alloca won't
satisfy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122233 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122232 91177308-0d34-0410-b5e6-96231b3b80d8
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out-edges. Fixes PR8824.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122228 91177308-0d34-0410-b5e6-96231b3b80d8
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begin at DEF slots. Fixes the second half of PR8813.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122225 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122224 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122222 91177308-0d34-0410-b5e6-96231b3b80d8
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ARM (and other 32-bit-only) targets support for i8 and i16 overflow
multiplies. The generated code isn't great, but this at least fixes
CodeGen/Generic/overflow.ll when running on ARM hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122221 91177308-0d34-0410-b5e6-96231b3b80d8
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the same as setcc. Optimize ADDC(0,0,FLAGS) -> SET_CARRY(FLAGS). This is
a step towards finishing off PR5443. In the testcase in that bug we now get:
movq %rdi, %rax
addq %rsi, %rax
sbbq %rcx, %rcx
testb $1, %cl
setne %dl
ret
instead of:
movq %rdi, %rax
addq %rsi, %rax
movl $0, %ecx
adcq $0, %rcx
testq %rcx, %rcx
setne %dl
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122219 91177308-0d34-0410-b5e6-96231b3b80d8
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the register; it may be a dead def instead. Fixes PR8820.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122218 91177308-0d34-0410-b5e6-96231b3b80d8
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doesn't, match it back to setb.
On a 64-bit version of the testcase before we'd get:
movq %rdi, %rax
addq %rsi, %rax
sbbb %dl, %dl
andb $1, %dl
ret
now we get:
movq %rdi, %rax
addq %rsi, %rax
setb %dl
ret
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122215 91177308-0d34-0410-b5e6-96231b3b80d8
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their carry depenedencies with MVT::Flag operands) and use clean and beautiful
EFLAGS dependences instead.
We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs
(which is what requires the previous scheduler change) and change X86 ISelLowering
to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes.
With the previous series of changes, this causes no changes in the testsuite, woo.
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Imagine we see:
EFLAGS = inst1
EFLAGS = inst2 FLAGS
gpr = inst3 EFLAGS
Previously, we would refuse to schedule inst2 because it clobbers
the EFLAGS of the predecessor. However, it also uses the EFLAGS
of the predecessor, so it is safe to emit. SDep edges ensure that
the right order happens already anyway.
This fixes 2 testsuite crashes with the X86 patch I'm going to
commit next.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122210 91177308-0d34-0410-b5e6-96231b3b80d8
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PR8822.
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after legalize types
has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type.
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half of PR8813.
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ConnectedVNInfoEqClasses::Classify().
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consistently by moving it out of lowering into dag combine.
Add some missing patterns for matching away extended versions of setcc_c.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122199 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122197 91177308-0d34-0410-b5e6-96231b3b80d8
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going through the CSE maps to get it.
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headers provide symbols outside namespace std and the LLVM coding standards
state that we should prefix all of them.
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enough to teach it that ADDE(0,0) is known 0 except the
low bit, for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122191 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122190 91177308-0d34-0410-b5e6-96231b3b80d8
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we don't need -disable-mmx anymore.
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tests don't need -disable-mmx.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122187 91177308-0d34-0410-b5e6-96231b3b80d8
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generate them.
Now we compile:
define zeroext i8 @X(i8 signext %a, i8 signext %b) nounwind ssp {
entry:
%0 = tail call %0 @llvm.sadd.with.overflow.i8(i8 %a, i8 %b)
%cmp = extractvalue %0 %0, 1
br i1 %cmp, label %if.then, label %if.end
into:
_X: ## @X
## BB#0: ## %entry
subl $12, %esp
movb 16(%esp), %al
addb 20(%esp), %al
jo LBB0_2
Before we were generating:
_X: ## @X
## BB#0: ## %entry
pushl %ebp
movl %esp, %ebp
subl $8, %esp
movb 12(%ebp), %al
testb %al, %al
setge %cl
movb 8(%ebp), %dl
testb %dl, %dl
setge %ah
cmpb %cl, %ah
sete %cl
addb %al, %dl
testb %dl, %dl
setge %al
cmpb %al, %ah
setne %al
andb %cl, %al
testb %al, %al
jne LBB0_2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122186 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122183 91177308-0d34-0410-b5e6-96231b3b80d8
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