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2013-03-27R600/SI: add srl/sha patterns for SIChristian Konig
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178125 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27Allocate r0 on PPCHal Finkel
The R0 register can now be allocated because instructions that cannot use R0 as a GPR have been appropriately marked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27Use the PPC no-r0 class on the TOC LD pseudosHal Finkel
The register parameter in these instructions becomes the base register in an r+i ld instruction (and, thus, cannot be r0). This is not yet testable because we don't yet allocate r0 (and even then any test would be very fragile). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178121 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27Apply the no-r0 register class to the PPC SELECT_CC_I[4|8] pseudosHal Finkel
Either operand of these pseudo instructions can be transformed into the first operand of an isel instruction (and this operand cannot be r0). This is not yet testable because we don't yet allocate r0 (and even when we do, any test would be very fragile). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178119 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27Apply the no-r0 class to PPC TOC ADDI[S] pseudo instructionsHal Finkel
Like the addi/addis instructions themselves, these pseudo instructions also cannot have r0 as their register parameter (because it will be interpreted as the value 0). This is not yet testable because we don't yet allocate r0 (and even when we do, any regression test would be very fragile because it would depend on the register allocator heuristics). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27Remove the link register from the GPR classes on PowerPC.Bill Schmidt
Some implementation detail in the forgotten past required the link register to be placed in the GPRC and G8RC register classes. This is just wrong on the face of it, and causes several extra intersection register classes to be generated. I found this was having evil effects on instruction scheduling, by causing the wrong register class to be consulted for register pressure decisions. No code generation changes are expected, other than some minor changes in instruction order. Seven tests in the test bucket required minor tweaks to adjust to the new normal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178114 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27Added back in the test for arc-annotations.Michael Gottesman
The test was removed since I had not turned off the test during release builds. This fails since ARC annotations support is conditionally compiled out during release builds. I added the proper requires header to assuage this issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178101 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27Adding DIImportedModules to DIScopes.David Blaikie
This is just the basic groundwork for supporting DW_TAG_imported_module but I wanted to commit this before pushing support further into Clang or LLVM so that this rather churny change is isolated from the rest of the work. The major churn here is obviously adding another field (within the common DIScope prefix) to all DIScopes (files, classes, namespaces, lexical scopes, etc). This should be the last big churny change needed for DW_TAG_imported_module/using directive support/PR14606. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178099 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27Don't spill PPC VRSAVE on non-Darwin (even in SjLj)Hal Finkel
As Bill Schmidt pointed out to me, only on Darwin do we need to spill/restore VRSAVE in the SjLj code. For non-Darwin, don't spill/restore VRSAVE (and I've added some asserts to make sure that we're not). As it turns out, we're not currently handling the Darwin case correctly (I've added a FIXME in the test case). I've tried adding various implied register definitions/uses to force the spill without success, so I'll need to address this later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Make DIBuilder::createClassType more type safe by returning DICompositeType ↵David Blaikie
rather than DIType git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178091 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26DebugInfo: more support for mutating DICompositeType to reduce magic number ↵David Blaikie
usage in Clang git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178090 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Add a boolean parameter to the ExecuteAndWait static function to indicatedChad Rosier
if execution failed. ExecuteAndWait returns -1 upon an execution failure, but checking the return value isn't sufficient because the wait command may return -1 as well. This new parameter is to be used by the clang driver in a subsequent commit. Part of rdar://13362359 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178087 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Use the full path when outputting the `.gcda' file.Bill Wendling
If we compile a single source program, the `.gcda' file will be generated where the program was executed. This isn't desirable, because that place may be at an unpredictable place (the program could call `chdir' for instance). Instead, we will output the `.gcda' file in the same place we output the `.gcno' file. I.e., the directory where the executable was generated. This matches GCC's behavior. <rdar://problem/13061072> & PR11809 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178084 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Add XTEST codegen supportMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Add HLE target featureMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178082 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Enable SandyBridgeModel for all modern Intel P6 descendants.Jakob Stoklund Olesen
All Intel CPUs since Yonah look a lot alike, at least at the granularity of the scheduling models. We can add more accurate models for processors that aren't Sandy Bridge if required. Haswell will probably need its own. The Atom processor and anything based on NetBurst is completely different. So are the non-Intel chips. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178080 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Debug Info: Provide a means to update the members of a composite typeDavid Blaikie
This will be used to factor out some uses of magic number operand offsets inside Clang where these fields were updated in an effort to resolve forward declarations/circular references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Restore real bit lengths on PPC register numbersHal Finkel
As suggested by Bill Schmidt (in reviewing r178067), use the real register number bit lengths (which is self-documenting, and prevents using illegal numbers), and set only the relevant bits in HWEncoding (which defaults to 0). No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178077 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.Andrew Trick
Allow variants to be defined only for some processors on a target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178074 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Fix the register scavenger for targets that provide custom spillingHal Finkel
As pointed out by Richard Sandiford, my recent updates to the register scavenger broke targets that use custom spilling (because the new code assumed that if there were no valid spill slots, than spilling would be impossible). I don't have a test case, but it should be possible to create one for Thumb 1, Mips 16, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178073 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26PPC: Use HWEncoding and TRI->getEncodingValueHal Finkel
As pointed out by Jakob, we don't need to maintain a separate register-numbering table. Instead we should let TableGen generate the table for us from the information (already present) in PPCRegisterInfo.td. TRI->getEncodingValue is now used to access register-encoding values. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26R600/SIMCCodeEmitter.cpp: Prune a couple of unused members, STI and Ctx. ↵NAKAMURA Takumi
[-Wunused-private-field] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178065 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Use multiple virtual registers in PPC CR spillingHal Finkel
Now that the register scavenger can support multiple spill slots, and PEI can use virtual-register-based scavenging for multiple simultaneous registers, we can use a virtual register for the transfer register in the CR spilling code. This should eliminate the last place (outside of the prologue/epilogue) where we depend on the unconditional availability of the r0 register. We will soon be able to allocate it (in a somewhat restricted sense) as a GPR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178060 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Update PPCRegisterInfo's use of virtual registers to be SSAHal Finkel
PPC's use of PEI's virtual-register-based scavenging functionality had redefined the virtual registers (it was non-SSA). Now that PEI supports dealing with instructions with multiple virtual registers, this can be cleanup up to use multiple virtual registers and keep SSA form. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178059 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Update PEI's virtual-register-based scavenging to support multiple ↵Hal Finkel
simultaneous mappings The previous algorithm could not deal properly with scavenging multiple virtual registers because it kept only one live virtual -> physical mapping (and iterated through operands in order). Now we don't maintain a current mapping, but rather use replaceRegWith to completely remove the virtual register as soon as the mapping is established. In order to allow the register scavenger to return a physical register killed by an instruction for definition by that same instruction, we now call RS->forward(I) prior to eliminating virtual registers defined in I. This requires a minor update to forward to ignore virtual registers. These new features will be tested in forthcoming commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178058 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Annotate the remaining x86 instructions with SchedRW lists.Jakob Stoklund Olesen
Now all x86 instructions that have itinerary classes also have SchedRW lists. This is required before the new scheduling models can be used. There are still unannotated instructions remaining, but they don't have itinerary classes either. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178051 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Annotate x87 and mmx instructions with SchedRW lists.Jakob Stoklund Olesen
This only covers the instructions that were given itinerary classes for the Atom model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178050 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Annotate control instructions with SchedRW lists.Jakob Stoklund Olesen
This could definitely be more granular. I am not sure if it makes a difference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178049 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Annotate the rest of X86InstrInfo.td with SchedRW lists.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178048 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Fix PRFCHW test on non-x86 buildsMichael Liao
- 'prefetch' intrinsics are only lowered when SSE is available. On non-X86 builds, 'generic' CPU is used and stops lowering any prefetch intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178046 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26BasicAA: Only query twice if the result of the more general query was MayAliasArnold Schwaighofer
This is a compile time optimization. Before the patch we would do two traversals on each call to aliasGEP - one with a set size parameter one with UnknownSize. We can do better by first checking the result of the alias query with UnknownSize. Only if this one returns MayAlias do we query a second time using size and type. This recovers an about 7% compile time regression on spec/ammp. radar://12349960 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178045 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Add PREFETCHW codegen supportMichael Liao
- Add 'PRFCHW' feature defined in AVX2 ISA extension git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178040 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Add test case for commit r178031.Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178038 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Make InstCombineCasts.cpp:OptimizeIntToFloatBitCast endian safe.Ulrich Weigand
The OptimizeIntToFloatBitCast converts shift-truncate sequences into extractelement operations. The computation of the element index to be used in the resulting operation is currently only correct for little-endian targets. This commit fixes the element index computation to be correct for big-endian targets as well. If the target byte order is unknown, the optimization cannot be performed at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178031 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Hexagon: Remove HexagonMCInst.h file. It has been replaced with ↵Jyotsna Verma
MCTargetDesc/HexagonMCInst.h. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178030 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Revert ARM Scheduler Model: Add resources instructions, map resourcesArnold Schwaighofer
This reverts commit r177968. It is causing failures in a local build bot. "fatal error: error in backend: Expected a variant SchedClass" Original commit message: Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178028 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Remove default case from fully covered switch.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178025 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26R600/SI: improve post ISel foldingChristian Konig
Not only fold immediates, but avoid unnecessary copies as well. Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178024 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26R600/SI: improve vector interpolationChristian Konig
Prevent loading M0 multiple times. Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178023 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLEChristian Konig
Just define the address as unknown instead of VReg_32. Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178022 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26R600/SI: switch back to RegPressure schedulingChristian Konig
Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178021 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26R600/SI: mark most intrinsics as readnone v2Christian Konig
They read from constant register space anyway. v2: fix lit tests Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26R600/SI: replace WQM intrinsicChristian Konig
Just enable WQM when we see an LDS interpolation instruction. Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178019 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26R600/SI: fix ELSE pseudo op handlingChristian Konig
Restore the EXEC mask early, otherwise a copy might end up not beeing executed. Candidate for the mesa stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178018 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26Patch by Gordon Keiser!Joe Abbey
If PC or SP is the destination, the disassembler erroneously failed with the invalid encoding, despite the manual saying that both are fine. This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a postindexed load, where the offset 0xc is applied to SP after the load occurs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178017 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26[ASan] Change the ABI of __asan_before_dynamic_init function: now it takes ↵Alexey Samsonov
pointer to private string with module name. This string serves as a unique module ID in ASan runtime. LLVM part git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178013 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26PowerPC: Mark patterns as isCodeGenOnly.Ulrich Weigand
There remain a number of patterns that cannot (and should not) be handled by the asm parser, in particular all the Pseudo patterns. This commit marks those patterns as isCodeGenOnly. No change in generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178008 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26PowerPC: Simplify handling of fixups.Ulrich Weigand
MCTargetDesc/PPCMCCodeEmitter.cpp current has code like: if (isSVR4ABI() && is64BitMode()) Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_toc16)); else Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_lo16)); This is a problem for the asm parser, since it requires knowledge of the ABI / 64-bit mode to be set up. However, more fundamentally, at this point we shouldn't make such distinctions anyway; in an assembler file, it always ought to be possible to e.g. generate TOC relocations even when the main ABI is one that doesn't use TOC. Fortunately, this is actually completely unnecessary; that code was added to decide whether to generate TOC relocations, but that information is in fact already encoded in the VariantKind of the underlying symbol. This commit therefore merges those fixup types into one, and then decides which relocation to use based on the VariantKind. No changes in generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26PowerPC: Simplify FADD in round-to-zero mode.Ulrich Weigand
As part of the the sequence generated to implement long double -> int conversions, we need to perform an FADD in round-to-zero mode. This is problematical since the FPSCR is not at all modeled at the SelectionDAG level, and thus there is a risk of getting floating point instructions generated out of sequence with the instructions to modify FPSCR. The current code handles this by somewhat "special" patterns that in part have dummy operands, and/or duplicate existing instructions, making them awkward to handle in the asm parser. This commit changes this by leaving the "FADD in round-to-zero mode" as an atomic operation on the SelectionDAG level, and only split it up into real instructions at the MI level (via custom inserter). Since at *this* level the FPSCR *is* modeled (via the "RM" hard register), much of the "special" stuff can just go away, and the resulting patterns can be used by the asm parser. No significant change in generated code expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178006 91177308-0d34-0410-b5e6-96231b3b80d8
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