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AgeCommit message (Expand)Author
2012-05-11Revert 156658.Chad Rosier
2012-05-11[fast-isel] Fast-isel doesn't use the expect intrinsic.Chad Rosier
2012-05-11Use regular expression to match register names. Akira Hatanaka
2012-05-11Make the URL a link instead.Bill Wendling
2012-05-11[Support/StringRef] Add find_last_not_of and {r,l,}trim.Michael J. Spencer
2012-05-11Remove extraneous ; and the resulting warning.Bill Wendling
2012-05-11Add mention of Glasgow Haskell Compiler.Bill Wendling
2012-05-11[fast-isel] Add support for selecting @llvm.trap().Chad Rosier
2012-05-11Updated instruction table due to addded intrinsics.Brendon Cahoon
2012-05-11Remove warnings from HexagonVLIWPacketizer.Sirish Pande
2012-05-11Some release notes for dragonegg.Duncan Sands
2012-05-11Hexagon constant extender support.Brendon Cahoon
2012-05-11Typo.Chad Rosier
2012-05-11[fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Min...Chad Rosier
2012-05-11Hexagon V5 intrinsics support.Sirish Pande
2012-05-11Defer computation of SuperRegs.Jakob Stoklund Olesen
2012-05-11[fast-isel] Cleaner fix for when we're unable to handle a non-double multi-regChad Rosier
2012-05-11objectsize: add a few more tests and fix a bugNuno Lopes
2012-05-11[fast-isel] Rather then assert (or segfault in a non-asserts build), fall backChad Rosier
2012-05-11The return type is an unsigned, not a bool.Chad Rosier
2012-05-11Add space before an open parenthesis in control flow statements.Manman Ren
2012-05-11Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd
2012-05-11PR1255: ConstantRangesSet and CRSBuilder classes moved from include/llvm to i...Stepan Dyatkovskiy
2012-05-11Fix test/CodeGen/X86/tls-pie.ll.Hans Wennborg
2012-05-11Implement initial-exec TLS model for 32-bit PIC x86Hans Wennborg
2012-05-11Added the missing bit definition for the 4th bit of the STR (post reg) instru...Silviu Baranga
2012-05-11Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate o...Silviu Baranga
2012-05-11Fix a use after free when the streamer is destroyed. Fixes pr12622.Rafael Espindola
2012-05-11Fix a misleading comment.Akira Hatanaka
2012-05-11Tidy up. Trailing whitespace.Jim Grosbach
2012-05-11Tidy up. Trailing whitespace.Jim Grosbach
2012-05-11Fix a minor logic mistake transforming compares in instcombine. PR12514.Eli Friedman
2012-05-11ARM: peephole optimization to remove cmp instructionManman Ren
2012-05-11Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman
2012-05-11Allow unique_file to take a mode for file permissions, but defaultEric Christopher
2012-05-10Fix intendation.Chad Rosier
2012-05-10Compute secondary sub-registers.Jakob Stoklund Olesen
2012-05-10objectsize: add support for GEPs with non-constant indexesNuno Lopes
2012-05-10Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd
2012-05-10Add support for the 'X' inline asm operand modifier.Eric Christopher
2012-05-10misched: Print machineinstrs with -debug-only=mischedAndrew Trick
2012-05-10misched: tracing register pressure heuristics.Andrew Trick
2012-05-10misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick
2012-05-10misched: Release only unscheduled nodes into ReadyQ.Andrew Trick
2012-05-10misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick
2012-05-10misched: Introducing Top and Bottom register pressure trackers during schedul...Andrew Trick
2012-05-10Hexagon V5 Support - V5 td file.Sirish Pande
2012-05-10Hexagon V5 FP Support.Sirish Pande
2012-05-10RegPressure: API for speculatively checking instruction pressure.Andrew Trick
2012-05-10RegPressure: fix array index iteration style.Andrew Trick
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