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2013-04-26cleanup testcase some moreAdrian Prantl
rdar://problem/13056109 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180619 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26fix a typo that due to cu&paste quadrupled itselfAdrian Prantl
rdar://problem/13056109 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180618 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet
"hint" space for Thumb actually overlaps the encoding space of the CPS instruction. In actuality, hints can be defined as CPS instructions where imod and M bits are all nil. Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe, sev) in DecodeT2CPSInstruction. This commit adds a proper diagnostic message for Imm0_4 and updates all tests. Patch by Mihail Popa <Mihail.Popa@arm.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180617 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26Add missing ':'.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180616 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26Bugfix for the debug intrinsic handling in InstCombiner:Adrian Prantl
Since we can't guarantee that the original dbg.declare instrinsic is removed by LowerDbgDeclare(), we need to make sure that we are not inserting the same dbg.value intrinsic over and over. This removes tons of redundant DIEs when compiling optimized code. rdar://problem/13056109 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180615 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26PowerPC: Use RegisterOperand instead of RegisterClass operandsUlrich Weigand
In the default PowerPC assembler syntax, registers are specified simply by number, so they cannot be distinguished from immediate values (without looking at the opcode). This means that the default operand matching logic for the asm parser does not work, and we need to specify custom matchers. Since those can only be specified with RegisterOperand classes and not directly on the RegisterClass, all instructions patterns used by the asm parser need to use a RegisterOperand (instead of a RegisterClass) for all their register operands. This patch adds one RegisterOperand for each RegisterClass, using the same name as the class, just in lower case, and updates all instruction patterns to use RegisterOperand instead of RegisterClass operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26Re-write the address propagation code for pre-indexed loads/stores to take ↵Silviu Baranga
into account some previously misssed cases (PRE_DEC addressing mode, the offset and base address are swapped, etc). This should fix PR15581. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180609 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26PowerPC: Fix encoding of vsubcuw and vsum4sbs instructionsUlrich Weigand
When testing the asm parser, I noticed wrong encodings for the above instructions (wrong sub-opcodes). Tests will be added together with the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180608 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26PowerPC: Fix encoding of stfsu and stfdu instructionsUlrich Weigand
When testing the asm parser, I noticed wrong encodings for the above instructions (wrong sub-opcodes). Note that apparently the compiler currently never generates pre-inc instructions for floating point types for some reason ... Tests will be added together with the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180607 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26PowerPC: Fix encoding of rldimi and rldcl instructionsUlrich Weigand
When testing the asm parser, I noticed wrong encodings for the above instructions (wrong operand name in rldimi, wrong form and sub-opcode for rldcl). Tests will be added together with the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180606 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26PowerPC: Support PC-relative fixup_ppc_brcond14.Ulrich Weigand
When testing the asm parser, I ran into an error when using a conditional branch to an external symbol (this doesn't occur in compiler-generated code) due to missing support in PPCELFObjectWriter::getRelocTypeInner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180605 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26ARM/NEON: Pattern match vector integer abs to vabs.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180604 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26X86: Now that we have a canonical form for vector integer abs, match it into ↵Benjamin Kramer
pabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180600 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26DAGCombiner: Canonicalize vector integer abs in the same way we do it for ↵Benjamin Kramer
scalars. This already helps SSE2 x86 a lot because it lacks an efficient way to represent a vector select. The long term goal is to enable the backend to match a canonicalized pattern into a single instruction (e.g. vabs or pabs). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180597 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26LoopVectorizer: Calculate the number of pointers to disambiguate at runtime ↵Nadav Rotem
based on the numbers of reads and writes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180593 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26Use 'git svn find-rev' in git-svnrevert instead of shell script fu.Michael Gottesman
Thanks Chandler! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180592 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26Revert "[objc-arc] Added ImpreciseAutoreleaseSet to track autorelease calls ↵Michael Gottesman
that were once autoreleaseRV instructions." This reverts commit r180222. I think this might tie in with a different problem which will require a different approach potentially. I am reverting this in the case I need to go down that second path. My apologies for the noise. = /. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180590 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26Updated GettingStarted.rst so that it references utils/git-svn for git-svnup ↵Michael Gottesman
instead of catting it into the documentation itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180589 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26Added the scripts git-svnup/git-svnrevert to utils/git-svn.Michael Gottesman
It makes more sense to have git-svnup here than catting said file in the documentation (where we should rather point users to this directory). I included git-svnrevert as an additional gift to the community. I will update the documentation in a second commit later today. git-svnrevert takes in a git hash for a commit, looks up the svn revision for said commit and then creates the normal git revert commit message with the one liner message, except instead of saying Revert "<<<INSERT ONELINER HERE>>>" This reverts commit <<<INSERT GITHASH HERE>>> It says: Revert "<<<INSERT ONELINER HERE>>>" This reverts commit r<<<INSERT SVN REVISION HERE>>> so git hashes will not escape into our svn logs (which just look unseemly). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180587 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Mips assembler: .set reorder supportJack Carter
Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180584 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Remove SMLoc paired with CHECK-NOT patterns. Not functionality change.Michael Liao
Pattern has source location by itself. After adding a trivial method to retrieve it, it's unnecessary to pair a source location for CHECK-NOT patterns. One thing revised after this is the diagnostic info is more accurate by pointing to the start of the CHECK-NOT pattern instead of the end of the CHECK-NOT pattern. E.g. diagnostic message previously looks like <stdin>:1:1: error: CHECK-NOT: string occurred! test ^ test.txt:1:16: note: CHECK-NOT: pattern specified here CHECK-NOT: test ^ is changed to <stdin>:1:1: error: CHECK-NOT: string occurred! test ^ test.txt:1:12: note: CHECK-NOT: pattern specified here CHECK-NOT: test ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180578 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Make function documentation conform to llvm standards.Preston Gurd
Expunge all remaining traces and use of live variable information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180577 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25ARM cost model: Integer div and rem is lowered to a function callArnold Schwaighofer
Reflect this in the cost model. I observed this in MiBench/consumer-lame. radar://13354716 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180576 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Re-enabling MCJIT object caching with memory leak fixedAndrew Kaylor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180575 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25revert r179735, it has no testcases, and doesn't really make sense.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180574 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25This patch adds the X86FixupLEAs pass, which will reduce instructionPreston Gurd
latency for certain models of the Intel Atom family, by converting instructions into their equivalent LEA instructions, when it is both useful and possible to do so. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180573 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25LoopVectorizer: No need to generate pointer disambiguation checks between ↵Nadav Rotem
readonly pointers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180570 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25[mc-coff] Forward Linker Option flags into the .drectve sectionReid Kleckner
Summary: This is modelled on the Mach-O linker options implementation and should support a Clang implementation of #pragma comment(lib/linker). Reviewers: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D724 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Fix section relocation for SECTIONREL32 with immediate offset.Rafael Espindola
Patch by Kai Nacke. This matches the gnu as output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180568 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Remove tailing whitespacesMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180564 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25[inline asm] Add a test case for r180226. The specific issue is that the inlineChad Rosier
assembly is requesting a 64-bit register, which is invalid for i386. rdar://13731657 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180445 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Use a pointer as the relocation iterator.Rafael Espindola
Since the relocation iterator walks only the relocations in one section, we can just use a pointer and avoid fetching information about the section at every reference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180262 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Clarify getRelocationAddress x getRelocationOffset a bit.Rafael Espindola
getRelocationAddress is for dynamic libraries and executables, getRelocationOffset for relocatable objects. Mark the getRelocationAddress of COFF and MachO as not implemented yet. Add a test of ELF's. llvm-readobj -r now prints the same values as readelf -r. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180259 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Fix constant folding for one lane vector types. Constant folding one lane ↵Silviu Baranga
vector types not returns a vector instead of a scalar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180254 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Revert "Adding object caching support to MCJIT"Rafael Espindola
This reverts commit 07f03923137a91e3cca5d7fc075a22f8c9baf33a. Looks like it broke the valgrind bot: http://lab.llvm.org:8011/builders/llvm-x86_64-linux-vg_leak/builds/649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180249 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Revert "Exposing MCJIT through C API"Rafael Espindola
This reverts commit 8c31b298149ca3c3f2bbd9e8aa9a01c4d91f3d74. It looks like this commit broke some bots: http://lab.llvm.org:8011/builders/llvm-ppc64-linux2/builds/5209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180248 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Don't compute a std::vector<uint8_t> just to write it out a stream.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180247 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Test case for r180241.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180246 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Test case for r180238.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180245 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25[mips] Add definitions of micromips load and store instructions.Akira Hatanaka
Patch by Zoran Jovanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180241 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Allow users to choose identity used to sign tools.Filipe Cabecinhas
Summary: No change if the identity isn't defined by the makefile. Reviewers: echristo Differential Revision: http://llvm-reviews.chandlerc.com/D632 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180240 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25[mips] Add definitions of micromips shift instructions.Akira Hatanaka
Patch by Zoran Jovanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-25Fixing OCAML bindings for MCJITAndrew Kaylor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180232 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24R600: Initialize BooleanVectorContentsTom Stellard
Fixes test/CodeGen/R600/setcc.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180231 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24R600: Use SHT_PROGBITS for the .AMDGPU.config sectionTom Stellard
The libelf implementation that is distributed here: http://www.mr511.de/software/english.html will not parse sections that are marked SHT_NULL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24Exposing MCJIT through C APIAndrew Kaylor
Patch by Filip Pizlo git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24Fix for r180193 - MI Sched: eliminate local vreg.Andrew Trick
Fixes PR15838. Need to check for blocks with nothing but dbg.value. I'm not sure how to force this situation with a unit test. I tried to reduce the test case in PR15838 (1k lines of metadata) but gave up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24[inline asm] Fix a crasher for an invalid value type/register class.Chad Rosier
rdar://13731657 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24Making invalidateInstructionCache automatic in SectionMemoryManagerAndrew Kaylor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180225 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24[objc-arc] Added ImpreciseAutoreleaseSet to track autorelease calls that ↵Michael Gottesman
were once autoreleaseRV instructions. Due to the semantics of ARC, we must be extremely conservative with autorelease calls inserted by the frontend since ARC gaurantees that said object will be in the autorelease pool after that point, an optimization invariant that the optimizer must respect. On the other hand, we are allowed significantly more flexibility with autoreleaseRV instructions. Often times though this flexibility is disrupted by early transformations which transform objc_autoreleaseRV => objc_autorelease if said instruction is no longer being used as part of an RV pair (generally due to inlining). Since we can not tell the difference in between an autorelease put into place by the frontend and one created through said ``strength reduction'' we can not perform these optimizations. The addition of this set gets around said issues by allowing us to differentiate in between said two cases. rdar://problem/13697741. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180222 91177308-0d34-0410-b5e6-96231b3b80d8
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