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2012-03-31Add a 2 byte safety margin in offset computations.Jakob Stoklund Olesen
ARMConstantIslandPass still has bugs where jump table compression can cause constant pool entries to go out of range. Add a safety margin of 2 bytes when placing constant islands, but use the real max displacement for verification. <rdar://problem/11156595> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153789 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-31Add more debugging output to ARMConstantIslandPass.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153788 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30* Set the scope attributes for the ASM symbol we added to be the value passedBill Wendling
into the function. * Reorder some header files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153783 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Rip out emission of the regIsInRegClass function for the asm printer.Benjamin Kramer
It's slow, bloated and completely redundant with MCRegisterClass::contains. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153782 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM fix encoding fixup resolution for ldrd and friends.Jim Grosbach
The 8-bit payload is not contiguous in the opcode. Move the upper nibble over 4 bits into the correct place. rdar://11158641 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153780 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Use SequenceToOffsetTable in emitRegisterNameString.Jakob Stoklund Olesen
This allows suffix sharing in register names. (AX is a suffix of EAX). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153777 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Reapply 153764 and 153761 with a fix.Jakob Stoklund Olesen
Use an explicit comparator instead of the default. The sets are sorted, but not using the default comparator. Hopefully, this will unbreak the Linux builders. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153772 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Revert 153764 and 153761. They broke a --enable-optimized --enable-assertionsRafael Espindola
--enable-expensive-checks build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153771 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM assembler should prefer non-aliases encoding of cmp.Jim Grosbach
When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg, we want to use the non-negated form to make sure we prefer the normal encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153770 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM encoding for VSWP got the second operand incorrect.Jim Grosbach
Make the non-tied register operand names line up with what the base class encoding handler expects. rdar://11157236 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM can only use narrow encoding for low regs.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153765 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Compress SimpleValueType lists by sharing.Jakob Stoklund Olesen
Many register classes have the same value types. Share the table space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Compress register lists by sharing suffixes.Jakob Stoklund Olesen
TableGen emits lists of sub-registers, super-registers, and overlaps. Put them all in a single table and use a SequenceToOffsetTable to share suffixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Add a SequenceToOffsetTable to TableGen.Jakob Stoklund Olesen
This is similar to the StringToOffsetTable we use to produce string tables, but it can be used for other sequences than strings, and it eliminates entries for suffixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM integrated assembler should encoding choice for add/sub imm.Jim Grosbach
For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2 can be used for this syntax. Prefer the narrow encoding when possible. rdar://11156277 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Handle unreachable code in the dominates functions. This changes users whenRafael Espindola
needed for correctness, but still doesn't clean up code that now unnecessary checks for reachability. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Re-factored RuntimeDyLd:Danil Malyshev
1. The main works will made in the RuntimeDyLdImpl with uses the ObjectFile class. RuntimeDyLdMachO and RuntimeDyLdELF now only parses relocations and resolve it. This is allows to make improvements of the RuntimeDyLd more easily. In addition the support for COFF can be easily added. 2. Added ARM relocations to RuntimeDyLdELF. 3. Added support for stub functions for the ARM, allowing to do a long branch. 4. Added support for external functions that are not loaded from the object files, but can be loaded from external libraries. Now MCJIT can correctly execute the code containing the printf, putc, and etc. 5. The sections emitted instead functions, thanks Jim Grosbach. MemoryManager.startFunctionBody() and MemoryManager.endFunctionBody() have been removed. 6. MCJITMemoryManager.allocateDataSection() and MCJITMemoryManager. allocateCodeSection() used JMM->allocateSpace() instead of JMM->allocateCodeSection() and JMM->allocateDataSection(), because I got an error: "Cannot allocate an allocated block!" with object file contains more than one code or data sections. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153754 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM assembly parsing needs to be paranoid about negative immediates.Jim Grosbach
Make sure to treat immediates as unsigned when doing relative comparisons. rdar://11153621 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153753 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Add computeMaskedBitsLoad back, as it was the change to instsimplify thatRafael Espindola
caused the slowdown last time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153747 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Add a note about a missed cmov -> sbb opportunity.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153741 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Cleanup whitespace. Doxygenize comments. And indent to llvm coding standards.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153740 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Ensure conditional BL instructions for ARM are given the fixup ↵James Molloy
fixup_arm_condbranch. Patch by Tim Northover! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM target should allow codegenprep to duplicate ret instructions to enable ↵Evan Cheng
tailcall opt. rdar://11140249 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153717 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Testcase for r153710.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153711 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30Add testcase for r153705Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153706 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30If we have a VLA that has a "use" in a metadata node that's then usedBill Wendling
here but it has no other uses, then we have a problem. E.g., int foo (const int *x) { char a[*x]; return 0; } If we assign 'a' a vreg and fast isel later on has to use the selection DAG isel, it will want to copy the value to the vreg. However, there are no uses, which goes counter to what selection DAG isel expects. <rdar://problem/11134152> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153705 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Change the constant in this testcase so that it results in a constant poolLang Hames
load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Revert r153694. It was causing failures in the buildbots.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153701 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Invalidate liveness in ARMConstantIslandPass.Jakob Stoklund Olesen
This pass splits basic blocks to insert constant islands, and it doesn't recompute the live-in lists. No later passes depend on accurate liveness information. This fixes PR12410 where the machine code verifier was complaining. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153700 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Prefer even-odd D-register pairs.Jakob Stoklund Olesen
We are sometimes allocatinog from the DPair register class which contains odd-even pairs in addition to the Q registers. Place the Q registers first in the DPair allocation order as they can be copied with a single instruction. The odd-even pairs should only be allocated as a last resort. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153699 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Filecheck-ize this test so that it actually tests something reasonable.Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153697 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Try using vmov.i32 to materialize FP32 constants that can't be materialized byLang Hames
vmov.f32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153696 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Re-factored RuntimeDyld.Danil Malyshev
Added ExecutionEngine/MCJIT tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153694 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Lowercase the tag name to match the rest of dwarf.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153691 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29ARM assembly 'cmp lr, #0' should not encode using 'cmn'.Jim Grosbach
The CMP->CMN alias was matching for an immediate of zero when it should only match for negative values. rdar://11129224 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29The shuffle scheduler is only available in asserts build - make misched-new.llLang Hames
testcase require asserts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Handle register copies for the new ARM register classes.Jakob Stoklund Olesen
ARM recently gained DPair, DTriple, and DQuad register classes. Update copyPhysReg() to handle copies in these register classes. No test case, it is difficult to make the register allocator emit the odd copies reliably. The missing DPair copy caused a failure on partialsums in the nightly test suite. <rdar://problem/11147997> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153686 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Drop O4 from the llc manpage, it was removed in r70445.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153684 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Make x86 REP_MOV* and REP_STO instructions use the correct operand sizes in ↵Lang Hames
64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153680 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Fix missed files in JIT unittests MakefileDanil Malyshev
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153672 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Expand FREM.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153671 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Add more constness to CodeGenRegisters.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153667 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Don't PRE compares.Jakob Stoklund Olesen
CodeGenPrepare sinks compare instructions down to their uses to prevent live flags and predicate registers across basic blocks. PRE of a compare instruction prevents that, forcing the i1 compare result into a general purpose register. That is usually more expensive than the redundant compare PRE was trying to eliminate in the first place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Replace assert(0) with llvm_unreachable to avoid warnings about dropping off ↵Benjamin Kramer
the end of a non-void function in Release builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153643 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Add support for objc property decls according to the page at:Eric Christopher
http://llvm.org/docs/SourceLevelDebugging.html#objcproperty including type and DECL. Expand the metadata needed accordingly. rdar://11144023 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153639 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Make some headway towards compiling all of LLVM.Bill Wendling
Module-level ASM may contain definitions of functions and globals. However, we were not telling the linker that these globals had definitions. As far as it was concerned, they were just declarations. Attempt to resolve this by inserting module-level ASM functions and globals into the '_symbol' set so that the linker will know that they have values. This gets us further towards our goal of compiling LLVM, but it still has problems when linking libLTO.dylib because of the `-dead_strip' flag that's passed to the linker. <rdar://problem/11124216> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153638 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Only allow symbolic names for (v)cmpss/sd/ps/pd encodings 8-31 to be used ↵Craig Topper
with 'v' version of instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153636 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29For X86, change load/dec-or-inc/store into dec-or-inc, respectively.Joel Jones
This is a code change to add support for changing instruction sequences of the form: load inc/dec of 8/16/32/64 bits store into the appropriate X86 inc/dec through memory instruction: inc[qlwb] / dec[qlwb] The checks that were in X86DAGToDAGISel::Select(SDNode *Node)>>ISD::STORE have been extracted to isLoadIncOrDecStore and reworked to use the better named wrappers for getOperand(unsigned) (e.g. getOffset()) and replaced Chain.getNode() with LoadNode. The comments have also been expanded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153635 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Cleanup whitespace.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Cache the end() iterator.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153632 91177308-0d34-0410-b5e6-96231b3b80d8
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