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bug fixes, and with improved heuristics for analyzing foreign-loop
addrecs.
This change also flattens IVUsers, eliminating the stride-oriented
groupings, which makes it easier to work with.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95975 91177308-0d34-0410-b5e6-96231b3b80d8
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costs.
* Enabled R1/R2 application for nodes with infinite spill costs in the Briggs heuristic (made
safe by the changes to the normalization proceedure).
* Removed a redundant header.
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This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.
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great solution for the disassembler, we'll go with "plan b".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95957 91177308-0d34-0410-b5e6-96231b3b80d8
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matcher is now free of implicit operands!
- Still need to clean up the code now that we don't to worry about implicit
operands, and to make it a hard error if an instruction fails to specify all
of its operands for some reason.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95956 91177308-0d34-0410-b5e6-96231b3b80d8
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MRRC, MRRc2. For disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95955 91177308-0d34-0410-b5e6-96231b3b80d8
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reduce down to a single value. InstCombine already does this transformation
but DAG legalization may introduce new opportunities. This has turned out to
be important for ARM where 64-bit values are split up during type legalization:
InstCombine is not able to remove the PHI cycles on the 64-bit values but
the separate 32-bit values can be optimized. I measured the compile time
impact of this (running llc on 176.gcc) and it was not significant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95951 91177308-0d34-0410-b5e6-96231b3b80d8
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with "tied memory operands", which is wrong.
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movq (%ecx,%edx,2), %xmm2
movhps (%ecx,%eax,2), %xmm2
rather than:
movq (%eax, %edx, 2), %xmm2
movq (%eax, %ebx, 2), %xmm3
movlhps %xmm3, %xmm2
Testcase forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95948 91177308-0d34-0410-b5e6-96231b3b80d8
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busted in both encoders. I'm not bothering to fix it in the
old one at this point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95947 91177308-0d34-0410-b5e6-96231b3b80d8
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Kees van Reeuwijk!
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implement support for it) that the stack should be forcibly realigned in the
prologue (and the process reversed in the epilogue).
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This time with fixed test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95938 91177308-0d34-0410-b5e6-96231b3b80d8
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testb %al, %al ## <MCInst #2412 TEST8rr
## <MCOperand Reg:2>
## <MCOperand Reg:2>>
jne LBB1_7 ## <MCInst #938 JNE_1
## <MCOperand Expr:(LBB1_7)>>
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implemented, llvm-mc --show-inst now uses it to print the
instruction opcode as well as the number.
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8 or 32-bit immediates, which allows the new encoder to handle
them.
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the tables to be const. Teach MCCodeEmitter to handle
the target-indep kinds so that we don't crash on them.
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tiny interval.
Also avoid division by zero.
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that generates the 1-byte and 4-byte immediate versions
from one definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95902 91177308-0d34-0410-b5e6-96231b3b80d8
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use a multipattern that generates both the 1-byte and 4-byte
versions from the same defm
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work anyway (Interpreter::getPointerToFunction doesn't return a
callable pointer), and improve the error message when an
ExecutionEngine can't be created.
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VFP).
Sorry!
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same dead instruction.
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A8.6.297
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Use SmallVector instead of std::vector for better speed when indirectbr has
few successors.
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symbols.
Thanks to Duncan Sands for the testcase!
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as the "Permanently UNDEFINED" instruction.
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fixes the remaining x86-64 jit failures afaik.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95867 91177308-0d34-0410-b5e6-96231b3b80d8
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r12b, etc) also encodes to a R/M value of 4, which is just
as illegal as ESP/RSP for the non-sib version an address.
This fixes x86-64 jit miscompilations of a bunch of programs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95866 91177308-0d34-0410-b5e6-96231b3b80d8
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Stub out some dummy fixups to make things work.
We can now emit fixups like this:
subl $20, %esp ## encoding: [0x83,0xec,A]
## fixup A - offset: 2, value: 20, kind: fixup_1byte_imm
Emitting $20 as a single-byte fixup to be later resolved
by the assembler is ridiculous of course (vs just emitting
the byte) but this is a failure of the matcher, which
should be producing an imm of 20, not an MCExpr of 20.
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and rename it to EmitImmediate.
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