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-rw-r--r--test/MC/AArch64/gicv3-regs-diagnostics.s61
-rw-r--r--test/MC/AArch64/gicv3-regs.s223
-rw-r--r--test/MC/ARM/2013-03-18-Br-to-label-named-like-reg.s5
-rw-r--r--test/MC/Disassembler/AArch64/gicv3-regs.txt222
-rw-r--r--test/MC/Disassembler/ARM/thumb2.txt5
-rw-r--r--test/MC/Disassembler/X86/simple-tests.txt15
-rw-r--r--test/MC/Mips/eh-frame.ll (renamed from test/MC/Mips/ef_frame.ll)0
-rw-r--r--test/MC/Mips/eh-frame.s46
-rw-r--r--test/MC/Mips/fde-reloc.s21
-rw-r--r--test/MC/Mips/mips-alu-instructions.s2
-rw-r--r--test/MC/Mips/mips-expansions.s22
-rw-r--r--test/MC/Mips/mips-jump-instructions.s40
-rw-r--r--test/MC/Mips/mips_directives.s6
-rw-r--r--test/MC/X86/fde-reloc.s11
-rw-r--r--test/MC/X86/intel-syntax-encoding.s21
-rw-r--r--test/MC/X86/x86-32-ms-inline-asm.s20
-rw-r--r--test/MC/X86/x86_64-fma4-encoding.s4
-rw-r--r--test/MC/X86/x86_64-rand-encoding.s49
-rw-r--r--test/MC/X86/x86_64-rtm-encoding.s4
19 files changed, 764 insertions, 13 deletions
diff --git a/test/MC/AArch64/gicv3-regs-diagnostics.s b/test/MC/AArch64/gicv3-regs-diagnostics.s
new file mode 100644
index 0000000000..e891adbbb3
--- /dev/null
+++ b/test/MC/AArch64/gicv3-regs-diagnostics.s
@@ -0,0 +1,61 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s
+
+ // Write-only
+ mrs x10, icc_eoir1_el1
+ mrs x7, icc_eoir0_el1
+ mrs x22, icc_dir_el1
+ mrs x24, icc_sgi1r_el1
+ mrs x8, icc_asgi1r_el1
+ mrs x28, icc_sgi0r_el1
+// CHECK: error: expected readable system register
+// CHECK-NEXT: mrs x10, icc_eoir1_el1
+// CHECK-NEXT: ^
+// CHECK-NEXT: error: expected readable system register
+// CHECK-NEXT: mrs x7, icc_eoir0_el1
+// CHECK-NEXT: ^
+// CHECK-NEXT: error: expected readable system register
+// CHECK-NEXT: mrs x22, icc_dir_el1
+// CHECK-NEXT: ^
+// CHECK-NEXT: error: expected readable system register
+// CHECK-NEXT: mrs x24, icc_sgi1r_el1
+// CHECK-NEXT: ^
+// CHECK-NEXT: error: expected readable system register
+// CHECK-NEXT: mrs x8, icc_asgi1r_el1
+// CHECK-NEXT: ^
+// CHECK-NEXT: error: expected readable system register
+// CHECK-NEXT: mrs x28, icc_sgi0r_el1
+// CHECK-NEXT: ^
+
+ // Read-only
+ msr icc_iar1_el1, x16
+ msr icc_iar0_el1, x19
+ msr icc_hppir1_el1, x29
+ msr icc_hppir0_el1, x14
+ msr icc_rpr_el1, x6
+ msr ich_vtr_el2, x8
+ msr ich_eisr_el2, x22
+ msr ich_elsr_el2, x8
+// CHECK: error: expected writable system register or pstate
+// CHECK-NEXT: msr icc_iar1_el1, x16
+// CHECK-NEXT: ^
+// CHECK-NEXT: error: expected writable system register or pstate
+// CHECK-NEXT: msr icc_iar0_el1, x19
+// CHECK-NEXT: ^
+// CHECK-NEXT: error: expected writable system register or pstate
+// CHECK-NEXT: msr icc_hppir1_el1, x29
+// CHECK-NEXT: ^
+// CHECK-NEXT: error: expected writable system register or pstate
+// CHECK-NEXT: msr icc_hppir0_el1, x14
+// CHECK-NEXT: ^
+// CHECK-NEXT: error: expected writable system register or pstate
+// CHECK-NEXT: msr icc_rpr_el1, x6
+// CHECK-NEXT: ^
+// CHECK-NEXT: error: expected writable system register or pstate
+// CHECK-NEXT: msr ich_vtr_el2, x8
+// CHECK-NEXT: ^
+// CHECK-NEXT: error: expected writable system register or pstate
+// CHECK-NEXT: msr ich_eisr_el2, x22
+// CHECK-NEXT: ^
+// CHECK-NEXT: error: expected writable system register or pstate
+// CHECK-NEXT: msr ich_elsr_el2, x8
+// CHECK-NEXT: ^
diff --git a/test/MC/AArch64/gicv3-regs.s b/test/MC/AArch64/gicv3-regs.s
new file mode 100644
index 0000000000..f7776514da
--- /dev/null
+++ b/test/MC/AArch64/gicv3-regs.s
@@ -0,0 +1,223 @@
+ // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
+
+ mrs x8, icc_iar1_el1
+ mrs x26, icc_iar0_el1
+ mrs x2, icc_hppir1_el1
+ mrs x17, icc_hppir0_el1
+ mrs x29, icc_rpr_el1
+ mrs x4, ich_vtr_el2
+ mrs x24, ich_eisr_el2
+ mrs x9, ich_elsr_el2
+ mrs x24, icc_bpr1_el1
+ mrs x14, icc_bpr0_el1
+ mrs x19, icc_pmr_el1
+ mrs x23, icc_ctlr_el1
+ mrs x20, icc_ctlr_el3
+ mrs x28, icc_sre_el1
+ mrs x25, icc_sre_el2
+ mrs x8, icc_sre_el3
+ mrs x22, icc_igrpen0_el1
+ mrs x5, icc_igrpen1_el1
+ mrs x7, icc_igrpen1_el3
+ mrs x22, icc_seien_el1
+ mrs x4, icc_ap0r0_el1
+ mrs x11, icc_ap0r1_el1
+ mrs x27, icc_ap0r2_el1
+ mrs x21, icc_ap0r3_el1
+ mrs x2, icc_ap1r0_el1
+ mrs x21, icc_ap1r1_el1
+ mrs x10, icc_ap1r2_el1
+ mrs x27, icc_ap1r3_el1
+ mrs x20, ich_ap0r0_el2
+ mrs x21, ich_ap0r1_el2
+ mrs x5, ich_ap0r2_el2
+ mrs x4, ich_ap0r3_el2
+ mrs x15, ich_ap1r0_el2
+ mrs x12, ich_ap1r1_el2
+ mrs x27, ich_ap1r2_el2
+ mrs x20, ich_ap1r3_el2
+ mrs x10, ich_hcr_el2
+ mrs x27, ich_misr_el2
+ mrs x6, ich_vmcr_el2
+ mrs x19, ich_vseir_el2
+ mrs x3, ich_lr0_el2
+ mrs x1, ich_lr1_el2
+ mrs x22, ich_lr2_el2
+ mrs x21, ich_lr3_el2
+ mrs x6, ich_lr4_el2
+ mrs x10, ich_lr5_el2
+ mrs x11, ich_lr6_el2
+ mrs x12, ich_lr7_el2
+ mrs x0, ich_lr8_el2
+ mrs x21, ich_lr9_el2
+ mrs x13, ich_lr10_el2
+ mrs x26, ich_lr11_el2
+ mrs x1, ich_lr12_el2
+ mrs x8, ich_lr13_el2
+ mrs x2, ich_lr14_el2
+ mrs x8, ich_lr15_el2
+// CHECK: mrs x8, icc_iar1_el1 // encoding: [0x08,0xcc,0x38,0xd5]
+// CHECK: mrs x26, icc_iar0_el1 // encoding: [0x1a,0xc8,0x38,0xd5]
+// CHECK: mrs x2, icc_hppir1_el1 // encoding: [0x42,0xcc,0x38,0xd5]
+// CHECK: mrs x17, icc_hppir0_el1 // encoding: [0x51,0xc8,0x38,0xd5]
+// CHECK: mrs x29, icc_rpr_el1 // encoding: [0x7d,0xcb,0x38,0xd5]
+// CHECK: mrs x4, ich_vtr_el2 // encoding: [0x24,0xcb,0x3c,0xd5]
+// CHECK: mrs x24, ich_eisr_el2 // encoding: [0x78,0xcb,0x3c,0xd5]
+// CHECK: mrs x9, ich_elsr_el2 // encoding: [0xa9,0xcb,0x3c,0xd5]
+// CHECK: mrs x24, icc_bpr1_el1 // encoding: [0x78,0xcc,0x38,0xd5]
+// CHECK: mrs x14, icc_bpr0_el1 // encoding: [0x6e,0xc8,0x38,0xd5]
+// CHECK: mrs x19, icc_pmr_el1 // encoding: [0x13,0x46,0x38,0xd5]
+// CHECK: mrs x23, icc_ctlr_el1 // encoding: [0x97,0xcc,0x38,0xd5]
+// CHECK: mrs x20, icc_ctlr_el3 // encoding: [0x94,0xcc,0x3e,0xd5]
+// CHECK: mrs x28, icc_sre_el1 // encoding: [0xbc,0xcc,0x38,0xd5]
+// CHECK: mrs x25, icc_sre_el2 // encoding: [0xb9,0xc9,0x3c,0xd5]
+// CHECK: mrs x8, icc_sre_el3 // encoding: [0xa8,0xcc,0x3e,0xd5]
+// CHECK: mrs x22, icc_igrpen0_el1 // encoding: [0xd6,0xcc,0x38,0xd5]
+// CHECK: mrs x5, icc_igrpen1_el1 // encoding: [0xe5,0xcc,0x38,0xd5]
+// CHECK: mrs x7, icc_igrpen1_el3 // encoding: [0xe7,0xcc,0x3e,0xd5]
+// CHECK: mrs x22, icc_seien_el1 // encoding: [0x16,0xcd,0x38,0xd5]
+// CHECK: mrs x4, icc_ap0r0_el1 // encoding: [0x84,0xc8,0x38,0xd5]
+// CHECK: mrs x11, icc_ap0r1_el1 // encoding: [0xab,0xc8,0x38,0xd5]
+// CHECK: mrs x27, icc_ap0r2_el1 // encoding: [0xdb,0xc8,0x38,0xd5]
+// CHECK: mrs x21, icc_ap0r3_el1 // encoding: [0xf5,0xc8,0x38,0xd5]
+// CHECK: mrs x2, icc_ap1r0_el1 // encoding: [0x02,0xc9,0x38,0xd5]
+// CHECK: mrs x21, icc_ap1r1_el1 // encoding: [0x35,0xc9,0x38,0xd5]
+// CHECK: mrs x10, icc_ap1r2_el1 // encoding: [0x4a,0xc9,0x38,0xd5]
+// CHECK: mrs x27, icc_ap1r3_el1 // encoding: [0x7b,0xc9,0x38,0xd5]
+// CHECK: mrs x20, ich_ap0r0_el2 // encoding: [0x14,0xc8,0x3c,0xd5]
+// CHECK: mrs x21, ich_ap0r1_el2 // encoding: [0x35,0xc8,0x3c,0xd5]
+// CHECK: mrs x5, ich_ap0r2_el2 // encoding: [0x45,0xc8,0x3c,0xd5]
+// CHECK: mrs x4, ich_ap0r3_el2 // encoding: [0x64,0xc8,0x3c,0xd5]
+// CHECK: mrs x15, ich_ap1r0_el2 // encoding: [0x0f,0xc9,0x3c,0xd5]
+// CHECK: mrs x12, ich_ap1r1_el2 // encoding: [0x2c,0xc9,0x3c,0xd5]
+// CHECK: mrs x27, ich_ap1r2_el2 // encoding: [0x5b,0xc9,0x3c,0xd5]
+// CHECK: mrs x20, ich_ap1r3_el2 // encoding: [0x74,0xc9,0x3c,0xd5]
+// CHECK: mrs x10, ich_hcr_el2 // encoding: [0x0a,0xcb,0x3c,0xd5]
+// CHECK: mrs x27, ich_misr_el2 // encoding: [0x5b,0xcb,0x3c,0xd5]
+// CHECK: mrs x6, ich_vmcr_el2 // encoding: [0xe6,0xcb,0x3c,0xd5]
+// CHECK: mrs x19, ich_vseir_el2 // encoding: [0x93,0xc9,0x3c,0xd5]
+// CHECK: mrs x3, ich_lr0_el2 // encoding: [0x03,0xcc,0x3c,0xd5]
+// CHECK: mrs x1, ich_lr1_el2 // encoding: [0x21,0xcc,0x3c,0xd5]
+// CHECK: mrs x22, ich_lr2_el2 // encoding: [0x56,0xcc,0x3c,0xd5]
+// CHECK: mrs x21, ich_lr3_el2 // encoding: [0x75,0xcc,0x3c,0xd5]
+// CHECK: mrs x6, ich_lr4_el2 // encoding: [0x86,0xcc,0x3c,0xd5]
+// CHECK: mrs x10, ich_lr5_el2 // encoding: [0xaa,0xcc,0x3c,0xd5]
+// CHECK: mrs x11, ich_lr6_el2 // encoding: [0xcb,0xcc,0x3c,0xd5]
+// CHECK: mrs x12, ich_lr7_el2 // encoding: [0xec,0xcc,0x3c,0xd5]
+// CHECK: mrs x0, ich_lr8_el2 // encoding: [0x00,0xcd,0x3c,0xd5]
+// CHECK: mrs x21, ich_lr9_el2 // encoding: [0x35,0xcd,0x3c,0xd5]
+// CHECK: mrs x13, ich_lr10_el2 // encoding: [0x4d,0xcd,0x3c,0xd5]
+// CHECK: mrs x26, ich_lr11_el2 // encoding: [0x7a,0xcd,0x3c,0xd5]
+// CHECK: mrs x1, ich_lr12_el2 // encoding: [0x81,0xcd,0x3c,0xd5]
+// CHECK: mrs x8, ich_lr13_el2 // encoding: [0xa8,0xcd,0x3c,0xd5]
+// CHECK: mrs x2, ich_lr14_el2 // encoding: [0xc2,0xcd,0x3c,0xd5]
+// CHECK: mrs x8, ich_lr15_el2 // encoding: [0xe8,0xcd,0x3c,0xd5]
+
+ msr icc_eoir1_el1, x27
+ msr icc_eoir0_el1, x5
+ msr icc_dir_el1, x13
+ msr icc_sgi1r_el1, x21
+ msr icc_asgi1r_el1, x25
+ msr icc_sgi0r_el1, x28
+ msr icc_bpr1_el1, x7
+ msr icc_bpr0_el1, x9
+ msr icc_pmr_el1, x29
+ msr icc_ctlr_el1, x24
+ msr icc_ctlr_el3, x0
+ msr icc_sre_el1, x2
+ msr icc_sre_el2, x5
+ msr icc_sre_el3, x10
+ msr icc_igrpen0_el1, x22
+ msr icc_igrpen1_el1, x11
+ msr icc_igrpen1_el3, x8
+ msr icc_seien_el1, x4
+ msr icc_ap0r0_el1, x27
+ msr icc_ap0r1_el1, x5
+ msr icc_ap0r2_el1, x20
+ msr icc_ap0r3_el1, x0
+ msr icc_ap1r0_el1, x2
+ msr icc_ap1r1_el1, x29
+ msr icc_ap1r2_el1, x23
+ msr icc_ap1r3_el1, x11
+ msr ich_ap0r0_el2, x2
+ msr ich_ap0r1_el2, x27
+ msr ich_ap0r2_el2, x7
+ msr ich_ap0r3_el2, x1
+ msr ich_ap1r0_el2, x7
+ msr ich_ap1r1_el2, x12
+ msr ich_ap1r2_el2, x14
+ msr ich_ap1r3_el2, x13
+ msr ich_hcr_el2, x1
+ msr ich_misr_el2, x10
+ msr ich_vmcr_el2, x24
+ msr ich_vseir_el2, x29
+ msr ich_lr0_el2, x26
+ msr ich_lr1_el2, x9
+ msr ich_lr2_el2, x18
+ msr ich_lr3_el2, x26
+ msr ich_lr4_el2, x22
+ msr ich_lr5_el2, x26
+ msr ich_lr6_el2, x27
+ msr ich_lr7_el2, x8
+ msr ich_lr8_el2, x17
+ msr ich_lr9_el2, x19
+ msr ich_lr10_el2, x17
+ msr ich_lr11_el2, x5
+ msr ich_lr12_el2, x29
+ msr ich_lr13_el2, x2
+ msr ich_lr14_el2, x13
+ msr ich_lr15_el2, x27
+// CHECK: msr icc_eoir1_el1, x27 // encoding: [0x3b,0xcc,0x18,0xd5]
+// CHECK: msr icc_eoir0_el1, x5 // encoding: [0x25,0xc8,0x18,0xd5]
+// CHECK: msr icc_dir_el1, x13 // encoding: [0x2d,0xcb,0x18,0xd5]
+// CHECK: msr icc_sgi1r_el1, x21 // encoding: [0xb5,0xcb,0x18,0xd5]
+// CHECK: msr icc_asgi1r_el1, x25 // encoding: [0xd9,0xcb,0x18,0xd5]
+// CHECK: msr icc_sgi0r_el1, x28 // encoding: [0xfc,0xcb,0x18,0xd5]
+// CHECK: msr icc_bpr1_el1, x7 // encoding: [0x67,0xcc,0x18,0xd5]
+// CHECK: msr icc_bpr0_el1, x9 // encoding: [0x69,0xc8,0x18,0xd5]
+// CHECK: msr icc_pmr_el1, x29 // encoding: [0x1d,0x46,0x18,0xd5]
+// CHECK: msr icc_ctlr_el1, x24 // encoding: [0x98,0xcc,0x18,0xd5]
+// CHECK: msr icc_ctlr_el3, x0 // encoding: [0x80,0xcc,0x1e,0xd5]
+// CHECK: msr icc_sre_el1, x2 // encoding: [0xa2,0xcc,0x18,0xd5]
+// CHECK: msr icc_sre_el2, x5 // encoding: [0xa5,0xc9,0x1c,0xd5]
+// CHECK: msr icc_sre_el3, x10 // encoding: [0xaa,0xcc,0x1e,0xd5]
+// CHECK: msr icc_igrpen0_el1, x22 // encoding: [0xd6,0xcc,0x18,0xd5]
+// CHECK: msr icc_igrpen1_el1, x11 // encoding: [0xeb,0xcc,0x18,0xd5]
+// CHECK: msr icc_igrpen1_el3, x8 // encoding: [0xe8,0xcc,0x1e,0xd5]
+// CHECK: msr icc_seien_el1, x4 // encoding: [0x04,0xcd,0x18,0xd5]
+// CHECK: msr icc_ap0r0_el1, x27 // encoding: [0x9b,0xc8,0x18,0xd5]
+// CHECK: msr icc_ap0r1_el1, x5 // encoding: [0xa5,0xc8,0x18,0xd5]
+// CHECK: msr icc_ap0r2_el1, x20 // encoding: [0xd4,0xc8,0x18,0xd5]
+// CHECK: msr icc_ap0r3_el1, x0 // encoding: [0xe0,0xc8,0x18,0xd5]
+// CHECK: msr icc_ap1r0_el1, x2 // encoding: [0x02,0xc9,0x18,0xd5]
+// CHECK: msr icc_ap1r1_el1, x29 // encoding: [0x3d,0xc9,0x18,0xd5]
+// CHECK: msr icc_ap1r2_el1, x23 // encoding: [0x57,0xc9,0x18,0xd5]
+// CHECK: msr icc_ap1r3_el1, x11 // encoding: [0x6b,0xc9,0x18,0xd5]
+// CHECK: msr ich_ap0r0_el2, x2 // encoding: [0x02,0xc8,0x1c,0xd5]
+// CHECK: msr ich_ap0r1_el2, x27 // encoding: [0x3b,0xc8,0x1c,0xd5]
+// CHECK: msr ich_ap0r2_el2, x7 // encoding: [0x47,0xc8,0x1c,0xd5]
+// CHECK: msr ich_ap0r3_el2, x1 // encoding: [0x61,0xc8,0x1c,0xd5]
+// CHECK: msr ich_ap1r0_el2, x7 // encoding: [0x07,0xc9,0x1c,0xd5]
+// CHECK: msr ich_ap1r1_el2, x12 // encoding: [0x2c,0xc9,0x1c,0xd5]
+// CHECK: msr ich_ap1r2_el2, x14 // encoding: [0x4e,0xc9,0x1c,0xd5]
+// CHECK: msr ich_ap1r3_el2, x13 // encoding: [0x6d,0xc9,0x1c,0xd5]
+// CHECK: msr ich_hcr_el2, x1 // encoding: [0x01,0xcb,0x1c,0xd5]
+// CHECK: msr ich_misr_el2, x10 // encoding: [0x4a,0xcb,0x1c,0xd5]
+// CHECK: msr ich_vmcr_el2, x24 // encoding: [0xf8,0xcb,0x1c,0xd5]
+// CHECK: msr ich_vseir_el2, x29 // encoding: [0x9d,0xc9,0x1c,0xd5]
+// CHECK: msr ich_lr0_el2, x26 // encoding: [0x1a,0xcc,0x1c,0xd5]
+// CHECK: msr ich_lr1_el2, x9 // encoding: [0x29,0xcc,0x1c,0xd5]
+// CHECK: msr ich_lr2_el2, x18 // encoding: [0x52,0xcc,0x1c,0xd5]
+// CHECK: msr ich_lr3_el2, x26 // encoding: [0x7a,0xcc,0x1c,0xd5]
+// CHECK: msr ich_lr4_el2, x22 // encoding: [0x96,0xcc,0x1c,0xd5]
+// CHECK: msr ich_lr5_el2, x26 // encoding: [0xba,0xcc,0x1c,0xd5]
+// CHECK: msr ich_lr6_el2, x27 // encoding: [0xdb,0xcc,0x1c,0xd5]
+// CHECK: msr ich_lr7_el2, x8 // encoding: [0xe8,0xcc,0x1c,0xd5]
+// CHECK: msr ich_lr8_el2, x17 // encoding: [0x11,0xcd,0x1c,0xd5]
+// CHECK: msr ich_lr9_el2, x19 // encoding: [0x33,0xcd,0x1c,0xd5]
+// CHECK: msr ich_lr10_el2, x17 // encoding: [0x51,0xcd,0x1c,0xd5]
+// CHECK: msr ich_lr11_el2, x5 // encoding: [0x65,0xcd,0x1c,0xd5]
+// CHECK: msr ich_lr12_el2, x29 // encoding: [0x9d,0xcd,0x1c,0xd5]
+// CHECK: msr ich_lr13_el2, x2 // encoding: [0xa2,0xcd,0x1c,0xd5]
+// CHECK: msr ich_lr14_el2, x13 // encoding: [0xcd,0xcd,0x1c,0xd5]
+// CHECK: msr ich_lr15_el2, x27 // encoding: [0xfb,0xcd,0x1c,0xd5]
diff --git a/test/MC/ARM/2013-03-18-Br-to-label-named-like-reg.s b/test/MC/ARM/2013-03-18-Br-to-label-named-like-reg.s
new file mode 100644
index 0000000000..172abcf6f8
--- /dev/null
+++ b/test/MC/ARM/2013-03-18-Br-to-label-named-like-reg.s
@@ -0,0 +1,5 @@
+@ RUN: llvm-mc -arch arm %s
+@ CHECK: test:
+@ CHECK: br r1
+test:
+ bl r1
diff --git a/test/MC/Disassembler/AArch64/gicv3-regs.txt b/test/MC/Disassembler/AArch64/gicv3-regs.txt
new file mode 100644
index 0000000000..4351f6460c
--- /dev/null
+++ b/test/MC/Disassembler/AArch64/gicv3-regs.txt
@@ -0,0 +1,222 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s
+
+0x8 0xcc 0x38 0xd5
+# CHECK: mrs x8, icc_iar1_el1
+0x1a 0xc8 0x38 0xd5
+# CHECK: mrs x26, icc_iar0_el1
+0x42 0xcc 0x38 0xd5
+# CHECK: mrs x2, icc_hppir1_el1
+0x51 0xc8 0x38 0xd5
+# CHECK: mrs x17, icc_hppir0_el1
+0x7d 0xcb 0x38 0xd5
+# CHECK: mrs x29, icc_rpr_el1
+0x24 0xcb 0x3c 0xd5
+# CHECK: mrs x4, ich_vtr_el2
+0x78 0xcb 0x3c 0xd5
+# CHECK: mrs x24, ich_eisr_el2
+0xa9 0xcb 0x3c 0xd5
+# CHECK: mrs x9, ich_elsr_el2
+0x78 0xcc 0x38 0xd5
+# CHECK: mrs x24, icc_bpr1_el1
+0x6e 0xc8 0x38 0xd5
+# CHECK: mrs x14, icc_bpr0_el1
+0x13 0x46 0x38 0xd5
+# CHECK: mrs x19, icc_pmr_el1
+0x97 0xcc 0x38 0xd5
+# CHECK: mrs x23, icc_ctlr_el1
+0x94 0xcc 0x3e 0xd5
+# CHECK: mrs x20, icc_ctlr_el3
+0xbc 0xcc 0x38 0xd5
+# CHECK: mrs x28, icc_sre_el1
+0xb9 0xc9 0x3c 0xd5
+# CHECK: mrs x25, icc_sre_el2
+0xa8 0xcc 0x3e 0xd5
+# CHECK: mrs x8, icc_sre_el3
+0xd6 0xcc 0x38 0xd5
+# CHECK: mrs x22, icc_igrpen0_el1
+0xe5 0xcc 0x38 0xd5
+# CHECK: mrs x5, icc_igrpen1_el1
+0xe7 0xcc 0x3e 0xd5
+# CHECK: mrs x7, icc_igrpen1_el3
+0x16 0xcd 0x38 0xd5
+# CHECK: mrs x22, icc_seien_el1
+0x84 0xc8 0x38 0xd5
+# CHECK: mrs x4, icc_ap0r0_el1
+0xab 0xc8 0x38 0xd5
+# CHECK: mrs x11, icc_ap0r1_el1
+0xdb 0xc8 0x38 0xd5
+# CHECK: mrs x27, icc_ap0r2_el1
+0xf5 0xc8 0x38 0xd5
+# CHECK: mrs x21, icc_ap0r3_el1
+0x2 0xc9 0x38 0xd5
+# CHECK: mrs x2, icc_ap1r0_el1
+0x35 0xc9 0x38 0xd5
+# CHECK: mrs x21, icc_ap1r1_el1
+0x4a 0xc9 0x38 0xd5
+# CHECK: mrs x10, icc_ap1r2_el1
+0x7b 0xc9 0x38 0xd5
+# CHECK: mrs x27, icc_ap1r3_el1
+0x14 0xc8 0x3c 0xd5
+# CHECK: mrs x20, ich_ap0r0_el2
+0x35 0xc8 0x3c 0xd5
+# CHECK: mrs x21, ich_ap0r1_el2
+0x45 0xc8 0x3c 0xd5
+# CHECK: mrs x5, ich_ap0r2_el2
+0x64 0xc8 0x3c 0xd5
+# CHECK: mrs x4, ich_ap0r3_el2
+0xf 0xc9 0x3c 0xd5
+# CHECK: mrs x15, ich_ap1r0_el2
+0x2c 0xc9 0x3c 0xd5
+# CHECK: mrs x12, ich_ap1r1_el2
+0x5b 0xc9 0x3c 0xd5
+# CHECK: mrs x27, ich_ap1r2_el2
+0x74 0xc9 0x3c 0xd5
+# CHECK: mrs x20, ich_ap1r3_el2
+0xa 0xcb 0x3c 0xd5
+# CHECK: mrs x10, ich_hcr_el2
+0x5b 0xcb 0x3c 0xd5
+# CHECK: mrs x27, ich_misr_el2
+0xe6 0xcb 0x3c 0xd5
+# CHECK: mrs x6, ich_vmcr_el2
+0x93 0xc9 0x3c 0xd5
+# CHECK: mrs x19, ich_vseir_el2
+0x3 0xcc 0x3c 0xd5
+# CHECK: mrs x3, ich_lr0_el2
+0x21 0xcc 0x3c 0xd5
+# CHECK: mrs x1, ich_lr1_el2
+0x56 0xcc 0x3c 0xd5
+# CHECK: mrs x22, ich_lr2_el2
+0x75 0xcc 0x3c 0xd5
+# CHECK: mrs x21, ich_lr3_el2
+0x86 0xcc 0x3c 0xd5
+# CHECK: mrs x6, ich_lr4_el2
+0xaa 0xcc 0x3c 0xd5
+# CHECK: mrs x10, ich_lr5_el2
+0xcb 0xcc 0x3c 0xd5
+# CHECK: mrs x11, ich_lr6_el2
+0xec 0xcc 0x3c 0xd5
+# CHECK: mrs x12, ich_lr7_el2
+0x0 0xcd 0x3c 0xd5
+# CHECK: mrs x0, ich_lr8_el2
+0x35 0xcd 0x3c 0xd5
+# CHECK: mrs x21, ich_lr9_el2
+0x4d 0xcd 0x3c 0xd5
+# CHECK: mrs x13, ich_lr10_el2
+0x7a 0xcd 0x3c 0xd5
+# CHECK: mrs x26, ich_lr11_el2
+0x81 0xcd 0x3c 0xd5
+# CHECK: mrs x1, ich_lr12_el2
+0xa8 0xcd 0x3c 0xd5
+# CHECK: mrs x8, ich_lr13_el2
+0xc2 0xcd 0x3c 0xd5
+# CHECK: mrs x2, ich_lr14_el2
+0xe8 0xcd 0x3c 0xd5
+# CHECK: mrs x8, ich_lr15_el2
+0x3b 0xcc 0x18 0xd5
+# CHECK: msr icc_eoir1_el1, x27
+0x25 0xc8 0x18 0xd5
+# CHECK: msr icc_eoir0_el1, x5
+0x2d 0xcb 0x18 0xd5
+# CHECK: msr icc_dir_el1, x13
+0xb5 0xcb 0x18 0xd5
+# CHECK: msr icc_sgi1r_el1, x21
+0xd9 0xcb 0x18 0xd5
+# CHECK: msr icc_asgi1r_el1, x25
+0xfc 0xcb 0x18 0xd5
+# CHECK: msr icc_sgi0r_el1, x28
+0x67 0xcc 0x18 0xd5
+# CHECK: msr icc_bpr1_el1, x7
+0x69 0xc8 0x18 0xd5
+# CHECK: msr icc_bpr0_el1, x9
+0x1d 0x46 0x18 0xd5
+# CHECK: msr icc_pmr_el1, x29
+0x98 0xcc 0x18 0xd5
+# CHECK: msr icc_ctlr_el1, x24
+0x80 0xcc 0x1e 0xd5
+# CHECK: msr icc_ctlr_el3, x0
+0xa2 0xcc 0x18 0xd5
+# CHECK: msr icc_sre_el1, x2
+0xa5 0xc9 0x1c 0xd5
+# CHECK: msr icc_sre_el2, x5
+0xaa 0xcc 0x1e 0xd5
+# CHECK: msr icc_sre_el3, x10
+0xd6 0xcc 0x18 0xd5
+# CHECK: msr icc_igrpen0_el1, x22
+0xeb 0xcc 0x18 0xd5
+# CHECK: msr icc_igrpen1_el1, x11
+0xe8 0xcc 0x1e 0xd5
+# CHECK: msr icc_igrpen1_el3, x8
+0x4 0xcd 0x18 0xd5
+# CHECK: msr icc_seien_el1, x4
+0x9b 0xc8 0x18 0xd5
+# CHECK: msr icc_ap0r0_el1, x27
+0xa5 0xc8 0x18 0xd5
+# CHECK: msr icc_ap0r1_el1, x5
+0xd4 0xc8 0x18 0xd5
+# CHECK: msr icc_ap0r2_el1, x20
+0xe0 0xc8 0x18 0xd5
+# CHECK: msr icc_ap0r3_el1, x0
+0x2 0xc9 0x18 0xd5
+# CHECK: msr icc_ap1r0_el1, x2
+0x3d 0xc9 0x18 0xd5
+# CHECK: msr icc_ap1r1_el1, x29
+0x57 0xc9 0x18 0xd5
+# CHECK: msr icc_ap1r2_el1, x23
+0x6b 0xc9 0x18 0xd5
+# CHECK: msr icc_ap1r3_el1, x11
+0x2 0xc8 0x1c 0xd5
+# CHECK: msr ich_ap0r0_el2, x2
+0x3b 0xc8 0x1c 0xd5
+# CHECK: msr ich_ap0r1_el2, x27
+0x47 0xc8 0x1c 0xd5
+# CHECK: msr ich_ap0r2_el2, x7
+0x61 0xc8 0x1c 0xd5
+# CHECK: msr ich_ap0r3_el2, x1
+0x7 0xc9 0x1c 0xd5
+# CHECK: msr ich_ap1r0_el2, x7
+0x2c 0xc9 0x1c 0xd5
+# CHECK: msr ich_ap1r1_el2, x12
+0x4e 0xc9 0x1c 0xd5
+# CHECK: msr ich_ap1r2_el2, x14
+0x6d 0xc9 0x1c 0xd5
+# CHECK: msr ich_ap1r3_el2, x13
+0x1 0xcb 0x1c 0xd5
+# CHECK: msr ich_hcr_el2, x1
+0x4a 0xcb 0x1c 0xd5
+# CHECK: msr ich_misr_el2, x10
+0xf8 0xcb 0x1c 0xd5
+# CHECK: msr ich_vmcr_el2, x24
+0x9d 0xc9 0x1c 0xd5
+# CHECK: msr ich_vseir_el2, x29
+0x1a 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr0_el2, x26
+0x29 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr1_el2, x9
+0x52 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr2_el2, x18
+0x7a 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr3_el2, x26
+0x96 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr4_el2, x22
+0xba 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr5_el2, x26
+0xdb 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr6_el2, x27
+0xe8 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr7_el2, x8
+0x11 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr8_el2, x17
+0x33 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr9_el2, x19
+0x51 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr10_el2, x17
+0x65 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr11_el2, x5
+0x9d 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr12_el2, x29
+0xa2 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr13_el2, x2
+0xcd 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr14_el2, x13
+0xfb 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr15_el2, x27
diff --git a/test/MC/Disassembler/ARM/thumb2.txt b/test/MC/Disassembler/ARM/thumb2.txt
index 45dace3b09..31f75b39fa 100644
--- a/test/MC/Disassembler/ARM/thumb2.txt
+++ b/test/MC/Disassembler/ARM/thumb2.txt
@@ -254,9 +254,12 @@
#------------------------------------------------------------------------------
# CHECK: cbnz r7, #6
# CHECK: cbnz r7, #12
+# CHECK: cbz r4, #64
0x1f 0xb9
0x37 0xb9
+0x04 0xb3
+
#------------------------------------------------------------------------------
# CDP/CDP2
@@ -554,6 +557,7 @@
# CHECK: ldr.w r8, [r8, r2, lsl #2]
# CHECK: ldr.w r7, [sp, r2, lsl #1]
# CHECK: ldr.w r7, [sp, r2]
+# CHECK: ldr pc, [sp], #12
# CHECK: ldr r2, [r4, #255]!
# CHECK: ldr r8, [sp, #4]!
# CHECK: ldr lr, [sp, #-4]!
@@ -567,6 +571,7 @@
0x58 0xf8 0x22 0x80
0x5d 0xf8 0x12 0x70
0x5d 0xf8 0x02 0x70
+0x5d 0xf8 0x0c 0xfb
0x54 0xf8 0xff 0x2f
0x5d 0xf8 0x04 0x8f
0x5d 0xf8 0x04 0xed
diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt
index 5ea40eb913..9827a1809f 100644
--- a/test/MC/Disassembler/X86/simple-tests.txt
+++ b/test/MC/Disassembler/X86/simple-tests.txt
@@ -753,3 +753,18 @@
# CHECK: lock
# CHECK-NEXT: xaddq %rcx, %rbx
0xf0 0x48 0x0f 0xc1 0xcb
+
+# rdar://13493622 lldb doesn't print the x86 rep/repne prefix when disassembling
+# CHECK: repne
+# CHECK-NEXT: movsd
+0xf2 0xa5
+# CHECK: repne
+# CHECK-NEXT: movsq
+0xf2 0x48 0xa5
+# CHECK: repne
+# CHECK-NEXT: movb $0, (%rax)
+0xf2 0xc6 0x0 0x0
+# CHECK: rep
+# CHECK-NEXT: lock
+# CHECK-NEXT: incl (%rax)
+0xf3 0xf0 0xff 0x00
diff --git a/test/MC/Mips/ef_frame.ll b/test/MC/Mips/eh-frame.ll
index 91c8b43d02..91c8b43d02 100644
--- a/test/MC/Mips/ef_frame.ll
+++ b/test/MC/Mips/eh-frame.ll
diff --git a/test/MC/Mips/eh-frame.s b/test/MC/Mips/eh-frame.s
new file mode 100644
index 0000000000..56278b8b99
--- /dev/null
+++ b/test/MC/Mips/eh-frame.s
@@ -0,0 +1,46 @@
+// Assembler generated object test.
+// This tests .eh_frame descriptors minimally.
+
+// What we really need is a prettyprinter output check not unlike what
+// gnu's readobj generates instead of checking the bits for .eh_frame.
+
+// RUN: llvm-mc -filetype=obj -mcpu=mips32r2 -triple mipsel-unknown-linux -arch=mipsel %s -o - \
+// RUN: | llvm-objdump -s - | FileCheck -check-prefix=CHECK-LEO32 %s
+
+// RUN: llvm-mc -filetype=obj -mcpu=mips32r2 -triple mips-unknown-linux -arch=mips %s -o - \
+// RUN: | llvm-objdump -s - | FileCheck -check-prefix=CHECK-BEO32 %s
+
+// RUN: llvm-mc -filetype=obj -mcpu=mips64r2 -mattr=n64 -arch=mips64el %s -o - \
+// RUN: | llvm-objdump -s - | FileCheck -check-prefix=CHECK-LE64 %s
+
+// RUN: llvm-mc -filetype=obj -mcpu=mips64r2 -mattr=n64 -arch=mips64 %s -o - \
+// RUN: | llvm-objdump -s - | FileCheck -check-prefix=CHECK-BE64 %s
+
+// O32 little endian
+// CHECK-LEO32: Contents of section .eh_frame:
+// CHECK-LEO32-NEXT: 0000 10000000 00000000 017a5200 017c1f01 .........zR..|..
+// CHECK-LEO32-NEXT: 0010 000c1d00 10000000 18000000 00000000 ................
+// CHECK-LEO32-NEXT: 0020 00000000 00000000 ........
+
+// O32 big endian
+// CHECK-BEO32: Contents of section .eh_frame:
+// CHECK-BEO32-NEXT 0000 00000010 00000000 017a5200 017c1f01 .........zR..|..
+// CHECK-BEO32-NEXT 0010 000c1d00 00000010 00000018 00000000 ................
+// CHECK-BEO32-NEXT 0020 00000000 00000000 ........
+
+// N64 little endian
+// CHECK-LE64: Contents of section .eh_frame:
+// CHECK-LE64-NEXT: 0000 10000000 00000000 017a5200 01781f01 .........zR..x..
+// CHECK-LE64-NEXT: 0010 000c1d00 18000000 18000000 00000000 ................
+// CHECK-LE64-NEXT: 0020 00000000 00000000 00000000 00000000 ................
+
+// N64 big endian
+// CHECK-BE64: Contents of section .eh_frame:
+// CHECK-BE64-NEXT: 0000 00000010 00000000 017a5200 01781f01 .........zR..x..
+// CHECK-BE64-NEXT: 0010 000c1d00 00000018 00000018 00000000 ................
+// CHECK-BE64-NEXT: 0020 00000000 00000000 00000000 00000000 ................
+
+func:
+ .cfi_startproc
+ .cfi_endproc
+
diff --git a/test/MC/Mips/fde-reloc.s b/test/MC/Mips/fde-reloc.s
new file mode 100644
index 0000000000..2db5d0b638
--- /dev/null
+++ b/test/MC/Mips/fde-reloc.s
@@ -0,0 +1,21 @@
+// This just tests that a relocation of the specified type shows up as the first
+// relocation in the relocation section for .eh_frame when produced by the
+// assembler.
+
+// RUN: llvm-mc -filetype=obj %s -o - -triple mips-unknown-unknown | \
+// RUN: llvm-objdump -r - | FileCheck --check-prefix=MIPS32 %s
+
+// RUN: llvm-mc -filetype=obj %s -o - -triple mips64-unknown-unknown | \
+// RUN: llvm-objdump -r - | FileCheck --check-prefix=MIPS64 %s
+
+// PR15448
+
+func:
+ .cfi_startproc
+ .cfi_endproc
+
+// MIPS32: RELOCATION RECORDS FOR [.eh_frame]:
+// MIPS32-NEXT: R_MIPS_32
+
+// MIPS64: RELOCATION RECORDS FOR [.eh_frame]:
+// MIPS64-NEXT: R_MIPS_64
diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s
index 816138ec65..7384d19e44 100644
--- a/test/MC/Mips/mips-alu-instructions.s
+++ b/test/MC/Mips/mips-alu-instructions.s
@@ -13,6 +13,7 @@
# CHECK: ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d]
# CHECK: nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00]
# CHECK: or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00]
+# CHECK: ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34]
# CHECK: ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34]
# CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00]
# CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
@@ -40,6 +41,7 @@
ins $19, $9, 6,7
nor $9, $6, $7
or $3, $3, $5
+ or $4, $5, 17767
ori $9, $6, 17767
rotr $9, $6, 7
rotrv $9, $6, $7
diff --git a/test/MC/Mips/mips-expansions.s b/test/MC/Mips/mips-expansions.s
index cfc15e883a..3385fe1930 100644
--- a/test/MC/Mips/mips-expansions.s
+++ b/test/MC/Mips/mips-expansions.s
@@ -16,6 +16,22 @@
# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c]
# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34]
# CHECK: addu $7, $7, $8 # encoding: [0x21,0x38,0xe8,0x00]
+# CHECK: lui $10, %hi(symbol) # encoding: [A,A,0x0a,0x3c]
+# CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
+# CHECK: addu $10, $10, $4 # encoding: [0x21,0x50,0x44,0x01]
+# CHECK: lw $10, %lo(symbol)($10) # encoding: [A,A,0x4a,0x8d]
+# CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
+# CHECK: lui $1, %hi(symbol) # encoding: [A,A,0x01,0x3c]
+# CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
+# CHECK: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00]
+# CHECK: sw $10, %lo(symbol)($1) # encoding: [A,A,0x2a,0xac]
+# CHECK: # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
+# CHECK: lui $10, 10 # encoding: [0x0a,0x00,0x0a,0x3c]
+# CHECK: addu $10, $10, $4 # encoding: [0x21,0x50,0x44,0x01]
+# CHECK: lw $10, 123($10) # encoding: [0x7b,0x00,0x4a,0x8d]
+# CHECK: lui $1, 2 # encoding: [0x02,0x00,0x01,0x3c]
+# CHECK: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00]
+# CHECK: sw $10, 57920($1) # encoding: [0x40,0xe2,0x2a,0xac]
li $5,123
li $6,-2345
@@ -25,3 +41,9 @@
la $7,65538
la $a0, 20($a1)
la $7,65538($8)
+
+ lw $t2, symbol($a0)
+ sw $t2, symbol($t1)
+
+ lw $t2, 655483($a0)
+ sw $t2, 123456($t1)
diff --git a/test/MC/Mips/mips-jump-instructions.s b/test/MC/Mips/mips-jump-instructions.s
index bc2d720398..1dcb287738 100644
--- a/test/MC/Mips/mips-jump-instructions.s
+++ b/test/MC/Mips/mips-jump-instructions.s
@@ -1,30 +1,34 @@
-# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | \
+# RUN: FileCheck %s
# Check that the assembler can handle the documented syntax
# for jumps and branches.
# CHECK: .section __TEXT,__text,regular,pure_instructions
#------------------------------------------------------------------------------
# Branch instructions
#------------------------------------------------------------------------------
-# CHECK: b 1332 # encoding: [0x34,0x05,0x00,0x10]
+# CHECK: b 1332 # encoding: [0x4d,0x01,0x00,0x10]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
-# CHECK: bc1f 1332 # encoding: [0x34,0x05,0x00,0x45]
+# CHECK: bc1f 1332 # encoding: [0x4d,0x01,0x00,0x45]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
-# CHECK: bc1t 1332 # encoding: [0x34,0x05,0x01,0x45]
+# CHECK: bc1t 1332 # encoding: [0x4d,0x01,0x01,0x45]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
-# CHECK: beq $9, $6, 1332 # encoding: [0x34,0x05,0x26,0x11]
+# CHECK: beq $9, $6, 1332 # encoding: [0x4d,0x01,0x26,0x11]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
-# CHECK: bgez $6, 1332 # encoding: [0x34,0x05,0xc1,0x04]
+# CHECK: bgez $6, 1332 # encoding: [0x4d,0x01,0xc1,0x04]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
-# CHECK: bgezal $6, 1332 # encoding: [0x34,0x05,0xd1,0x04]
+# CHECK: bgezal $6, 1332 # encoding: [0x4d,0x01,0xd1,0x04]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
-# CHECK: bgtz $6, 1332 # encoding: [0x34,0x05,0xc0,0x1c]
+# CHECK: bgtz $6, 1332 # encoding: [0x4d,0x01,0xc0,0x1c]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
-# CHECK: blez $6, 1332 # encoding: [0x34,0x05,0xc0,0x18]
+# CHECK: blez $6, 1332 # encoding: [0x4d,0x01,0xc0,0x18]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
-# CHECK: bne $9, $6, 1332 # encoding: [0x34,0x05,0x26,0x15]
+# CHECK: bne $9, $6, 1332 # encoding: [0x4d,0x01,0x26,0x15]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
-# CHECK: bal 1332 # encoding: [0x34,0x05,0x11,0x04]
+# CHECK: bal 1332 # encoding: [0x4d,0x01,0x11,0x04]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+
+.set noreorder
+
b 1332
nop
bc1f 1332
@@ -50,9 +54,9 @@ end_of_code:
#------------------------------------------------------------------------------
# Jump instructions
#------------------------------------------------------------------------------
-# CHECK: j 1328 # encoding: [0x30,0x05,0x00,0x08]
+# CHECK: j 1328 # encoding: [0x4c,0x01,0x00,0x08]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
-# CHECK: jal 1328 # encoding: [0x30,0x05,0x00,0x0c]
+# CHECK: jal 1328 # encoding: [0x4c,0x01,0x00,0x0c]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK: jalr $6 # encoding: [0x09,0xf8,0xc0,0x00]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
@@ -63,6 +67,11 @@ end_of_code:
# CHECK: jr $7 # encoding: [0x08,0x00,0xe0,0x00]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK: jr $7 # encoding: [0x08,0x00,0xe0,0x00]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: jalr $25 # encoding: [0x09,0xf8,0x20,0x03]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
+# CHECK: jalr $4, $25 # encoding: [0x09,0x20,0x20,0x03]
+# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
j 1328
@@ -78,3 +87,8 @@ end_of_code:
jr $7
nop
j $7
+ nop
+ jal $25
+ nop
+ jal $4,$25
+ nop
diff --git a/test/MC/Mips/mips_directives.s b/test/MC/Mips/mips_directives.s
index 65d584dfa8..df7e645633 100644
--- a/test/MC/Mips/mips_directives.s
+++ b/test/MC/Mips/mips_directives.s
@@ -17,3 +17,9 @@ $JTI0_0:
.set macro
.set reorder
.set at=$a0
+ .set STORE_MASK,$t7
+ .set FPU_MASK,$f7
+#CHECK: abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85]
+#CHECK: and $3, $15, $15 # encoding: [0x01,0xef,0x18,0x24]
+ abs.s $f6,FPU_MASK
+ and $3,$t7,STORE_MASK
diff --git a/test/MC/X86/fde-reloc.s b/test/MC/X86/fde-reloc.s
new file mode 100644
index 0000000000..63ac976621
--- /dev/null
+++ b/test/MC/X86/fde-reloc.s
@@ -0,0 +1,11 @@
+// RUN: llvm-mc -filetype=obj %s -o - -triple x86_64-pc-linux | llvm-objdump -r - | FileCheck --check-prefix=X86-64 %s
+// RUN: llvm-mc -filetype=obj %s -o - -triple i686-pc-linux | llvm-objdump -r - | FileCheck --check-prefix=I686 %s
+
+// PR15448
+
+func:
+ .cfi_startproc
+ .cfi_endproc
+
+// X86-64: R_X86_64_PC32
+// I686: R_386_PC32
diff --git a/test/MC/X86/intel-syntax-encoding.s b/test/MC/X86/intel-syntax-encoding.s
index 03b0551164..9806ac3802 100644
--- a/test/MC/X86/intel-syntax-encoding.s
+++ b/test/MC/X86/intel-syntax-encoding.s
@@ -31,6 +31,27 @@
// CHECK: encoding: [0x48,0x83,0xc0,0xf4]
add rax, -12
+// CHECK: encoding: [0x66,0x83,0xd0,0xf4]
+ adc ax, -12
+// CHECK: encoding: [0x83,0xd0,0xf4]
+ adc eax, -12
+// CHECK: encoding: [0x48,0x83,0xd0,0xf4]
+ adc rax, -12
+
+// CHECK: encoding: [0x66,0x83,0xd8,0xf4]
+ sbb ax, -12
+// CHECK: encoding: [0x83,0xd8,0xf4]
+ sbb eax, -12
+// CHECK: encoding: [0x48,0x83,0xd8,0xf4]
+ sbb rax, -12
+
+// CHECK: encoding: [0x66,0x83,0xf8,0xf4]
+ cmp ax, -12
+// CHECK: encoding: [0x83,0xf8,0xf4]
+ cmp eax, -12
+// CHECK: encoding: [0x48,0x83,0xf8,0xf4]
+ cmp rax, -12
+
LBB0_3:
// CHECK: encoding: [0xeb,A]
jmp LBB0_3
diff --git a/test/MC/X86/x86-32-ms-inline-asm.s b/test/MC/X86/x86-32-ms-inline-asm.s
index 5524c706cc..d912915c58 100644
--- a/test/MC/X86/x86-32-ms-inline-asm.s
+++ b/test/MC/X86/x86-32-ms-inline-asm.s
@@ -57,6 +57,26 @@ _t21: ## @t21
// CHECK: movl 4(%esi,%eax,2), %eax
// CHECK: # encoding: [0x8b,0x44,0x46,0x04]
+ mov eax, 4[esi + 2*eax + 4]
+// CHECK: movl 8(%esi,%eax,2), %eax
+// CHECK: # encoding: [0x8b,0x44,0x46,0x08]
+ mov eax, 4[esi][2*eax + 4]
+// CHECK: movl 8(%esi,%eax,2), %eax
+// CHECK: # encoding: [0x8b,0x44,0x46,0x08]
+ mov eax, 4[esi + 2*eax][4]
+// CHECK: movl 8(%esi,%eax,2), %eax
+// CHECK: # encoding: [0x8b,0x44,0x46,0x08]
+ mov eax, 4[esi][2*eax][4]
+// CHECK: movl 8(%esi,%eax,2), %eax
+// CHECK: # encoding: [0x8b,0x44,0x46,0x08]
+ mov eax, 4[esi][2*eax][4][8]
+// CHECK: movl 16(%esi,%eax,2), %eax
+// CHECK: # encoding: [0x8b,0x44,0x46,0x10]
+
+ prefetchnta 64[eax]
+// CHECK: prefetchnta 64(%eax)
+// CHECK: # encoding: [0x0f,0x18,0x40,0x40]
+
pusha
// CHECK: pushal
// CHECK: # encoding: [0x60]
diff --git a/test/MC/X86/x86_64-fma4-encoding.s b/test/MC/X86/x86_64-fma4-encoding.s
index f7ee351ab5..c9bd954e90 100644
--- a/test/MC/X86/x86_64-fma4-encoding.s
+++ b/test/MC/X86/x86_64-fma4-encoding.s
@@ -25,6 +25,10 @@
// CHECK: encoding: [0xc4,0xe3,0xf9,0x6b,0xc2,0x10]
vfmaddsd %xmm2, %xmm1, %xmm0, %xmm0
+// CHECK: vfmaddsd %xmm10, %xmm1, %xmm0, %xmm0
+// CHECK: encoding: [0xc4,0xc3,0xf9,0x6b,0xc2,0x10]
+ vfmaddsd %xmm10, %xmm1, %xmm0, %xmm0
+
// CHECK: vfmaddps (%rcx), %xmm1, %xmm0, %xmm0
// CHECK: encoding: [0xc4,0xe3,0xf9,0x68,0x01,0x10]
vfmaddps (%rcx), %xmm1, %xmm0, %xmm0
diff --git a/test/MC/X86/x86_64-rand-encoding.s b/test/MC/X86/x86_64-rand-encoding.s
new file mode 100644
index 0000000000..3a8cb817bc
--- /dev/null
+++ b/test/MC/X86/x86_64-rand-encoding.s
@@ -0,0 +1,49 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK: rdrandw %ax
+// CHECK: encoding: [0x66,0x0f,0xc7,0xf0]
+ rdrand %ax
+
+// CHECK: rdrandl %eax
+// CHECK: encoding: [0x0f,0xc7,0xf0]
+ rdrand %eax
+
+// CHECK: rdrandq %rax
+// CHECK: encoding: [0x48,0x0f,0xc7,0xf0]
+ rdrand %rax
+
+// CHECK: rdrandw %r11w
+// CHECK: encoding: [0x66,0x41,0x0f,0xc7,0xf3]
+ rdrand %r11w
+
+// CHECK: rdrandl %r11d
+// CHECK: encoding: [0x41,0x0f,0xc7,0xf3]
+ rdrand %r11d
+
+// CHECK: rdrandq %r11
+// CHECK: encoding: [0x49,0x0f,0xc7,0xf3]
+ rdrand %r11
+
+// CHECK: rdseedw %ax
+// CHECK: encoding: [0x66,0x0f,0xc7,0xf8]
+ rdseed %ax
+
+// CHECK: rdseedl %eax
+// CHECK: encoding: [0x0f,0xc7,0xf8]
+ rdseed %eax
+
+// CHECK: rdseedq %rax
+// CHECK: encoding: [0x48,0x0f,0xc7,0xf8]
+ rdseed %rax
+
+// CHECK: rdseedw %r11w
+// CHECK: encoding: [0x66,0x41,0x0f,0xc7,0xfb]
+ rdseed %r11w
+
+// CHECK: rdseedl %r11d
+// CHECK: encoding: [0x41,0x0f,0xc7,0xfb]
+ rdseed %r11d
+
+// CHECK: rdseedq %r11
+// CHECK: encoding: [0x49,0x0f,0xc7,0xfb]
+ rdseed %r11
diff --git a/test/MC/X86/x86_64-rtm-encoding.s b/test/MC/X86/x86_64-rtm-encoding.s
index 44d6bacb7f..d9975d67b3 100644
--- a/test/MC/X86/x86_64-rtm-encoding.s
+++ b/test/MC/X86/x86_64-rtm-encoding.s
@@ -8,6 +8,10 @@
// CHECK: encoding: [0x0f,0x01,0xd5]
xend
+// CHECK: xtest
+// CHECK: encoding: [0x0f,0x01,0xd6]
+ xtest
+
// CHECK: xabort
// CHECK: encoding: [0xc6,0xf8,0x0d]
xabort $13
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-11-21 20:47:55 +0000