diff options
Diffstat (limited to 'test/CodeGen')
59 files changed, 0 insertions, 7313 deletions
diff --git a/test/CodeGen/CellSPU/2009-01-01-BrCond.ll b/test/CodeGen/CellSPU/2009-01-01-BrCond.ll deleted file mode 100644 index 35422311c5..0000000000 --- a/test/CodeGen/CellSPU/2009-01-01-BrCond.ll +++ /dev/null @@ -1,31 +0,0 @@ -; RUN: llc < %s -march=cellspu -o - | grep brz -; PR3274 - -target datalayout = "E-p:32:32:128-i1:8:128-i8:8:128-i16:16:128-i32:32:128-i64:32:128-f32:32:128-f64:64:128-v64:64:64-v128:128:128-a0:0:128-s0:128:128" -target triple = "spu" - %struct.anon = type { i64 } - %struct.fp_number_type = type { i32, i32, i32, [4 x i8], %struct.anon } - -define double @__floatunsidf(i32 %arg_a) nounwind { -entry: - %in = alloca %struct.fp_number_type, align 16 - %0 = getelementptr %struct.fp_number_type* %in, i32 0, i32 1 - store i32 0, i32* %0, align 4 - %1 = icmp eq i32 %arg_a, 0 - %2 = getelementptr %struct.fp_number_type* %in, i32 0, i32 0 - br i1 %1, label %bb, label %bb1 - -bb: ; preds = %entry - store i32 2, i32* %2, align 8 - br label %bb7 - -bb1: ; preds = %entry - ret double 0.0 - -bb7: ; preds = %bb5, %bb1, %bb - ret double 1.0 -} - -; declare i32 @llvm.ctlz.i32(i32) nounwind readnone - -declare double @__pack_d(%struct.fp_number_type*) diff --git a/test/CodeGen/CellSPU/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/CellSPU/2010-04-07-DbgValueOtherTargets.ll deleted file mode 100644 index 401399face..0000000000 --- a/test/CodeGen/CellSPU/2010-04-07-DbgValueOtherTargets.ll +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: llc -O0 -march=cellspu -asm-verbose < %s | FileCheck %s -; Check that DEBUG_VALUE comments come through on a variety of targets. - -define i32 @main() nounwind ssp { -entry: -; CHECK: DEBUG_VALUE - call void @llvm.dbg.value(metadata !6, i64 0, metadata !7), !dbg !9 - ret i32 0, !dbg !10 -} - -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone - -declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone - -!llvm.dbg.sp = !{!0} - -!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 589865, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/x.c", metadata !"/Users/manav", metadata !"clang version 2.9 (trunk 120996)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] -!4 = metadata !{metadata !5} -!5 = metadata !{i32 589860, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 0} -!7 = metadata !{i32 590080, metadata !8, metadata !"i", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] -!8 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] -!9 = metadata !{i32 3, i32 11, metadata !8, null} -!10 = metadata !{i32 4, i32 2, metadata !8, null} - diff --git a/test/CodeGen/CellSPU/and_ops.ll b/test/CodeGen/CellSPU/and_ops.ll deleted file mode 100644 index 4203e91068..0000000000 --- a/test/CodeGen/CellSPU/and_ops.ll +++ /dev/null @@ -1,282 +0,0 @@ -; RUN: llc < %s -march=cellspu > %t1.s -; RUN: grep and %t1.s | count 234 -; RUN: grep andc %t1.s | count 85 -; RUN: grep andi %t1.s | count 37 -; RUN: grep andhi %t1.s | count 30 -; RUN: grep andbi %t1.s | count 4 - -; CellSPU legalization is over-sensitive to Legalize's traversal order. -; XFAIL: * - -target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" -target triple = "spu" - -; AND instruction generation: -define <4 x i32> @and_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) { - %A = and <4 x i32> %arg1, %arg2 - ret <4 x i32> %A -} - -define <4 x i32> @and_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) { - %A = and <4 x i32> %arg2, %arg1 - ret <4 x i32> %A -} - -define <8 x i16> @and_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) { - %A = and <8 x i16> %arg1, %arg2 - ret <8 x i16> %A -} - -define <8 x i16> @and_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) { - %A = and <8 x i16> %arg2, %arg1 - ret <8 x i16> %A -} - -define <16 x i8> @and_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) { - %A = and <16 x i8> %arg2, %arg1 - ret <16 x i8> %A -} - -define <16 x i8> @and_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) { - %A = and <16 x i8> %arg1, %arg2 - ret <16 x i8> %A -} - -define i32 @and_i32_1(i32 %arg1, i32 %arg2) { - %A = and i32 %arg2, %arg1 - ret i32 %A -} - -define i32 @and_i32_2(i32 %arg1, i32 %arg2) { - %A = and i32 %arg1, %arg2 - ret i32 %A -} - -define i16 @and_i16_1(i16 %arg1, i16 %arg2) { - %A = and i16 %arg2, %arg1 - ret i16 %A -} - -define i16 @and_i16_2(i16 %arg1, i16 %arg2) { - %A = and i16 %arg1, %arg2 - ret i16 %A -} - -define i8 @and_i8_1(i8 %arg1, i8 %arg2) { - %A = and i8 %arg2, %arg1 - ret i8 %A -} - -define i8 @and_i8_2(i8 %arg1, i8 %arg2) { - %A = and i8 %arg1, %arg2 - ret i8 %A -} - -; ANDC instruction generation: -define <4 x i32> @andc_v4i32_1(<4 x i32> %arg1, <4 x i32> %arg2) { - %A = xor <4 x i32> %arg2, < i32 -1, i32 -1, i32 -1, i32 -1 > - %B = and <4 x i32> %arg1, %A - ret <4 x i32> %B -} - -define <4 x i32> @andc_v4i32_2(<4 x i32> %arg1, <4 x i32> %arg2) { - %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 > - %B = and <4 x i32> %arg2, %A - ret <4 x i32> %B -} - -define <4 x i32> @andc_v4i32_3(<4 x i32> %arg1, <4 x i32> %arg2) { - %A = xor <4 x i32> %arg1, < i32 -1, i32 -1, i32 -1, i32 -1 > - %B = and <4 x i32> %A, %arg2 - ret <4 x i32> %B -} - -define <8 x i16> @andc_v8i16_1(<8 x i16> %arg1, <8 x i16> %arg2) { - %A = xor <8 x i16> %arg2, < i16 -1, i16 -1, i16 -1, i16 -1, - i16 -1, i16 -1, i16 -1, i16 -1 > - %B = and <8 x i16> %arg1, %A - ret <8 x i16> %B -} - -define <8 x i16> @andc_v8i16_2(<8 x i16> %arg1, <8 x i16> %arg2) { - %A = xor <8 x i16> %arg1, < i16 -1, i16 -1, i16 -1, i16 -1, - i16 -1, i16 -1, i16 -1, i16 -1 > - %B = and <8 x i16> %arg2, %A - ret <8 x i16> %B -} - -define <16 x i8> @andc_v16i8_1(<16 x i8> %arg1, <16 x i8> %arg2) { - %A = xor <16 x i8> %arg1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1 > - %B = and <16 x i8> %arg2, %A - ret <16 x i8> %B -} - -define <16 x i8> @andc_v16i8_2(<16 x i8> %arg1, <16 x i8> %arg2) { - %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1 > - %B = and <16 x i8> %arg1, %A - ret <16 x i8> %B -} - -define <16 x i8> @andc_v16i8_3(<16 x i8> %arg1, <16 x i8> %arg2) { - %A = xor <16 x i8> %arg2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, - i8 -1, i8 -1, i8 -1, i8 -1 > - %B = and <16 x i8> %A, %arg1 - ret <16 x i8> %B -} - -define i32 @andc_i32_1(i32 %arg1, i32 %arg2) { - %A = xor i32 %arg2, -1 - %B = and i32 %A, %arg1 - ret i32 %B -} - -define i32 @andc_i32_2(i32 %arg1, i32 %arg2) { - %A = xor i32 %arg1, -1 - %B = and i32 %A, %arg2 - ret i32 %B -} - -define i32 @andc_i32_3(i32 %arg1, i32 %arg2) { - %A = xor i32 %arg2, -1 - %B = and i32 %arg1, %A - ret i32 %B -} - -define i16 @andc_i16_1(i16 %arg1, i16 %arg2) { - %A = xor i16 %arg2, -1 - %B = and i16 %A, %arg1 - ret i16 %B -} - -define i16 @andc_i16_2(i16 %arg1, i16 %arg2) { - %A = xor i16 %arg1, -1 - %B = and i16 %A, %arg2 - ret i16 %B -} - -define i16 @andc_i16_3(i16 %arg1, i16 %arg2) { - %A = xor i16 %arg2, -1 - %B = and i16 %arg1, %A - ret i16 %B -} - -define i8 @andc_i8_1(i8 %arg1, i8 %arg2) { - %A = xor i8 %arg2, -1 - %B = and i8 %A, %arg1 - ret i8 %B -} - -define i8 @andc_i8_2(i8 %arg1, i8 %arg2) { - %A = xor i8 %arg1, -1 - %B = and i8 %A, %arg2 - ret i8 %B -} - -define i8 @andc_i8_3(i8 %arg1, i8 %arg2) { - %A = xor i8 %arg2, -1 - %B = and i8 %arg1, %A - ret i8 %B -} - -; ANDI instruction generation (i32 data type): -define <4 x i32> @andi_v4i32_1(<4 x i32> %in) { - %tmp2 = and <4 x i32> %in, < i32 511, i32 511, i32 511, i32 511 > - ret <4 x i32> %tmp2 -} - -define <4 x i32> @andi_v4i32_2(<4 x i32> %in) { - %tmp2 = and <4 x i32> %in, < i32 510, i32 510, i32 510, i32 510 > - ret <4 x i32> %tmp2 -} - -define <4 x i32> @andi_v4i32_3(<4 x i32> %in) { - %tmp2 = and <4 x i32> %in, < i32 -1, i32 -1, i32 -1, i32 -1 > - ret <4 x i32> %tmp2 -} - -define <4 x i32> @andi_v4i32_4(<4 x i32> %in) { - %tmp2 = and <4 x i32> %in, < i32 -512, i32 -512, i32 -512, i32 -512 > - ret <4 x i32> %tmp2 -} - -define zeroext i32 @andi_u32(i32 zeroext %in) { - %tmp37 = and i32 %in, 37 - ret i32 %tmp37 -} - -define signext i32 @andi_i32(i32 signext %in) { - %tmp38 = and i32 %in, 37 - ret i32 %tmp38 -} - -define i32 @andi_i32_1(i32 %in) { - %tmp37 = and i32 %in, 37 - ret i32 %tmp37 -} - -; ANDHI instruction generation (i16 data type): -define <8 x i16> @andhi_v8i16_1(<8 x i16> %in) { - %tmp2 = and <8 x i16> %in, < i16 511, i16 511, i16 511, i16 511, - i16 511, i16 511, i16 511, i16 511 > - ret <8 x i16> %tmp2 -} - -define <8 x i16> @andhi_v8i16_2(<8 x i16> %in) { - %tmp2 = and <8 x i16> %in, < i16 510, i16 510, i16 510, i16 510, - i16 510, i16 510, i16 510, i16 510 > - ret <8 x i16> %tmp2 -} - -define <8 x i16> @andhi_v8i16_3(<8 x i16> %in) { - %tmp2 = and <8 x i16> %in, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, - i16 -1, i16 -1, i16 -1 > - ret <8 x i16> %tmp2 -} - -define <8 x i16> @andhi_v8i16_4(<8 x i16> %in) { - %tmp2 = and <8 x i16> %in, < i16 -512, i16 -512, i16 -512, i16 -512, - i16 -512, i16 -512, i16 -512, i16 -512 > - ret <8 x i16> %tmp2 -} - -define zeroext i16 @andhi_u16(i16 zeroext %in) { - %tmp37 = and i16 %in, 37 ; <i16> [#uses=1] - ret i16 %tmp37 -} - -define signext i16 @andhi_i16(i16 signext %in) { - %tmp38 = and i16 %in, 37 ; <i16> [#uses=1] - ret i16 %tmp38 -} - -; i8 data type (s/b ANDBI if 8-bit registers were supported): -define <16 x i8> @and_v16i8(<16 x i8> %in) { - ; ANDBI generated for vector types - %tmp2 = and <16 x i8> %in, < i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, - i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, - i8 42, i8 42, i8 42, i8 42 > - ret <16 x i8> %tmp2 -} - -define zeroext i8 @and_u8(i8 zeroext %in) { - ; ANDBI generated: - %tmp37 = and i8 %in, 37 - ret i8 %tmp37 -} - -define signext i8 @and_sext8(i8 signext %in) { - ; ANDBI generated - %tmp38 = and i8 %in, 37 - ret i8 %tmp38 -} - -define i8 @and_i8(i8 %in) { - ; ANDBI generated - %tmp38 = and i8 %in, 205 - ret i8 %tmp38 -} diff --git a/test/CodeGen/CellSPU/arg_ret.ll b/test/CodeGen/CellSPU/arg_ret.ll deleted file mode 100644 index 7410b724d6..0000000000 --- a/test/CodeGen/CellSPU/arg_ret.ll +++ /dev/null @@ -1,34 +0,0 @@ -; Test parameter passing and return values -;RUN: llc --march=cellspu %s -o - | FileCheck %s - -; this fits into registers r3-r74 -%paramstruct = type { i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32, - i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32, - i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32, - i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32, - i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32, - i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32,i32} -define ccc i32 @test_regs( %paramstruct %prm ) -{ -;CHECK: lr $3, $74 -;CHECK: bi $lr - %1 = extractvalue %paramstruct %prm, 71 - ret i32 %1 -} - -define ccc i32 @test_regs_and_stack( %paramstruct %prm, i32 %stackprm ) -{ -;CHECK-NOT: a $3, $74, $75 - %1 = extractvalue %paramstruct %prm, 71 - %2 = add i32 %1, %stackprm - ret i32 %2 -} - -define ccc %paramstruct @test_return( i32 %param, %paramstruct %prm ) -{ -;CHECK: lqd {{\$[0-9]+}}, 80($sp) -;CHECK-NOT: ori {{\$[0-9]+, \$[0-9]+, 0}} -;CHECK: lr $3, $4 - ret %paramstruct %prm -} - diff --git a/test/CodeGen/CellSPU/bigstack.ll b/test/CodeGen/CellSPU/bigstack.ll deleted file mode 100644 index 63293e2aec..0000000000 --- a/test/CodeGen/CellSPU/bigstack.ll +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: llc < %s -march=cellspu -o %t1.s -; RUN: grep lqx %t1.s | count 3 -; RUN: grep il %t1.s | grep -v file | count 5 -; RUN: grep stqx %t1.s | count 1 - -define i32 @bigstack() nounwind { -entry: - %avar = alloca i32 - %big_data = alloca [2048 x i32] - store i32 3840, i32* %avar, align 4 - br label %return - -return: - %retval = load i32* %avar - ret i32 %retval -} - diff --git a/test/CodeGen/CellSPU/bss.ll b/test/CodeGen/CellSPU/bss.ll deleted file mode 100644 index 327800d09c..0000000000 --- a/test/CodeGen/CellSPU/bss.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: llc < %s -march=cellspu | FileCheck %s - -@bssVar = global i32 zeroinitializer -; CHECK: .section .bss -; CHECK-NEXT: .globl - -@localVar= internal global i32 zeroinitializer -; CHECK-NOT: .lcomm -; CHECK: .local -; CHECK-NEXT: .comm - diff --git a/test/CodeGen/CellSPU/call.ll b/test/CodeGen/CellSPU/call.ll deleted file mode 100644 index 11cf770145..0000000000 --- a/test/CodeGen/CellSPU/call.ll +++ /dev/null @@ -1,49 +0,0 @@ -; RUN: llc < %s -march=cellspu | FileCheck %s - -target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" -target triple = "spu" - -define i32 @main() { -entry: - %a = call i32 @stub_1(i32 1, float 0x400921FA00000000) - call void @extern_stub_1(i32 %a, i32 4) - ret i32 %a -} - -declare void @extern_stub_1(i32, i32) - -define i32 @stub_1(i32 %x, float %y) { - ; CHECK: il $3, 0 - ; CHECK: bi $lr -entry: - ret i32 0 -} - -; vararg call: ensure that all caller-saved registers are spilled to the -; stack: -define i32 @stub_2(...) { -entry: - ret i32 0 -} - -; check that struct is passed in r3-> -; assert this by changing the second field in the struct -%0 = type { i32, i32, i32 } -declare %0 @callee() -define %0 @test_structret() -{ -;CHECK: stqd $lr, 16($sp) -;CHECK: stqd $sp, -48($sp) -;CHECK: ai $sp, $sp, -48 -;CHECK: brasl $lr, callee - %rv = call %0 @callee() -;CHECK: ai $4, $4, 1 -;CHECK: lqd $lr, 64($sp) -;CHECK: ai $sp, $sp, 48 -;CHECK: bi $lr - %oldval = extractvalue %0 %rv, 1 - %newval = add i32 %oldval,1 - %newrv = insertvalue %0 %rv, i32 %newval, 1 - ret %0 %newrv -} - diff --git a/test/CodeGen/CellSPU/crash.ll b/test/CodeGen/CellSPU/crash.ll deleted file mode 100644 index cc2ab71db3..0000000000 --- a/test/CodeGen/CellSPU/crash.ll +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: llc %s -march=cellspu -o - -declare i8 @return_i8() -declare i16 @return_i16() -define void @testfunc() { - %rv1 = call i8 @return_i8() - %rv2 = call i16 @return_i16() - ret void -}
\ No newline at end of file diff --git a/test/CodeGen/CellSPU/ctpop.ll b/test/CodeGen/CellSPU/ctpop.ll deleted file mode 100644 index e1a6cd8292..0000000000 --- a/test/CodeGen/CellSPU/ctpop.ll +++ /dev/null @@ -1,30 +0,0 @@ -; RUN: llc < %s -march=cellspu > %t1.s -; RUN: grep cntb %t1.s | count 3 -; RUN: grep andi %t1.s | count 3 -; RUN: grep rotmi %t1.s | count 2 -; RUN: grep rothmi %t1.s | count 1 -target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" -target triple = "spu" - -declare i8 @llvm.ctpop.i8(i8) -declare i16 @llvm.ctpop.i16(i16) -declare i32 @llvm.ctpop.i32(i32) - -define i32 @test_i8(i8 %X) { - call i8 @llvm.ctpop.i8(i8 %X) - %Y = zext i8 %1 to i32 - ret i32 %Y -} - -define i32 @test_i16(i16 %X) { - call i16 @llvm.ctpop.i16(i16 %X) - %Y = zext i16 %1 to i32 - ret i32 %Y -} - -define i32 @test_i32(i32 %X) { - call i32 @llvm.ctpop.i32(i32 %X) - %Y = bitcast i32 %1 to i32 - ret i32 %Y -} - diff --git a/test/CodeGen/CellSPU/div_ops.ll b/test/CodeGen/CellSPU/div_ops.ll deleted file mode 100644 index 0c93d83ca7..0000000000 --- a/test/CodeGen/CellSPU/div_ops.ll +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: llc --march=cellspu %s -o - | FileCheck %s - -; signed division rounds towards zero, rotma don't. -define i32 @sdivide (i32 %val ) -{ -; CHECK: rotmai -; CHECK: rotmi -; CHECK: a -; CHECK: rotmai -; CHECK: bi $lr - %rv = sdiv i32 %val, 4 - ret i32 %rv -} - -define i32 @udivide (i32 %val ) -{ -; CHECK: rotmi -; CHECK: bi $lr - %rv = udiv i32 %val, 4 - ret i32 %rv -} - diff --git a/test/CodeGen/CellSPU/dp_farith.ll b/test/CodeGen/CellSPU/dp_farith.ll deleted file mode 100644 index 66bff3eb78..0000000000 --- a/test/CodeGen/CellSPU/dp_farith.ll +++ /dev/null @@ -1,102 +0,0 @@ -; RUN: llc < %s -march=cellspu > %t1.s -; RUN: grep dfa %t1.s | count 2 -; RUN: grep dfs %t1.s | count 2 -; RUN: grep dfm %t1.s | count 6 -; RUN: grep dfma %t1.s | count 2 -; RUN: grep dfms %t1.s | count 2 -; RUN: grep dfnms %t1.s | count 4 -; -; This file includes double precision floating point arithmetic instructions -target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" -target triple = "spu" - -define double @fadd(double %arg1, double %arg2) { - %A = fadd double %arg1, %arg2 - ret double %A -} - -define <2 x double> @fadd_vec(<2 x double> %arg1, <2 x double> %arg2) { - %A = fadd <2 x double> %arg1, %arg2 - ret <2 x double> %A -} - -define double @fsub(double %arg1, double %arg2) { |