diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86.td | 7 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 13 | ||||
| -rw-r--r-- | lib/Target/X86/X86Subtarget.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/X86/X86Subtarget.h | 5 |
4 files changed, 25 insertions, 1 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td index e87da56cc6..bf095017f8 100644 --- a/lib/Target/X86/X86.td +++ b/lib/Target/X86/X86.td @@ -134,6 +134,9 @@ def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb", def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", "PadShortFunctions", "true", "Pad short functions">; +def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect", + "CallRegIndirect", "true", + "Call register indirect">; //===----------------------------------------------------------------------===// // X86 processors supported. @@ -181,7 +184,9 @@ def : ProcessorModel<"penryn", SandyBridgeModel, def : ProcessorModel<"atom", AtomModel, [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B, FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP, - FeatureSlowDivide, FeaturePadShortFunctions]>; + FeatureSlowDivide, + FeatureCallRegIndirect, + FeaturePadShortFunctions]>; // "Arrandale" along with corei3 and corei5 def : ProcessorModel<"corei7", SandyBridgeModel, diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 9ef6a3bca0..0eaab0f818 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -2629,6 +2629,19 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, InFlag = Chain.getValue(1); } + // Use indirect reference through register, when CALL uses a memory reference. + if (Subtarget->callRegIndirect() && + Callee.getOpcode() == ISD::LOAD) { + const TargetRegisterClass *AddrRegClass = + getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); + MachineRegisterInfo &MRI = MF.getRegInfo(); + unsigned VReg = MRI.createVirtualRegister(AddrRegClass); + SDValue tempValue = DAG.getCopyFromReg(Callee, + dl, VReg, Callee.getValueType()); + Chain = DAG.getCopyToReg(Chain, dl, VReg, tempValue, InFlag); + InFlag = Chain.getValue(1); + } + Ops.push_back(Chain); Ops.push_back(Callee); diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp index 4b368b4901..6e66c1aa96 100644 --- a/lib/Target/X86/X86Subtarget.cpp +++ b/lib/Target/X86/X86Subtarget.cpp @@ -458,6 +458,7 @@ void X86Subtarget::initializeEnvironment() { HasSlowDivide = false; PostRAScheduler = false; PadShortFunctions = false; + CallRegIndirect = false; stackAlignment = 4; // FIXME: this is a known good value for Yonah. How about others? MaxInlineSizeThreshold = 128; diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h index 108ef0eb1c..cac3f579b0 100644 --- a/lib/Target/X86/X86Subtarget.h +++ b/lib/Target/X86/X86Subtarget.h @@ -159,6 +159,10 @@ protected: /// a stall when returning too early. bool PadShortFunctions; + /// CallRegIndirect - True if the Calls with memory reference should be converted + /// to a register-based indirect call. + bool CallRegIndirect; + /// stackAlignment - The minimum alignment known to hold of the stack frame on /// entry to the function and which must be maintained by every function. unsigned stackAlignment; @@ -269,6 +273,7 @@ public: bool useLeaForSP() const { return UseLeaForSP; } bool hasSlowDivide() const { return HasSlowDivide; } bool padShortFunctions() const { return PadShortFunctions; } + bool callRegIndirect() const { return CallRegIndirect; } bool isAtom() const { return X86ProcFamily == IntelAtom; } |