diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/AsmParser/X86AsmParser.cpp | 9 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrFPStack.td | 6 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSystem.td | 8 |
3 files changed, 14 insertions, 9 deletions
diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index 4aad817f13..975d46fadc 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -703,6 +703,7 @@ ParseInstruction(StringRef Name, SMLoc NameLoc, .Case("fwait", "wait") .Case("movzx", "movzb") // FIXME: Not correct. .Case("fildq", "fildll") + .Case("ud2a", "ud2") .Default(Name); // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}. @@ -1175,9 +1176,10 @@ MatchAndEmitInstruction(SMLoc IDLoc, // First, handle aliases that expand to multiple instructions. // FIXME: This should be replaced with a real .td file alias mechanism. - if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" || + if (Op->getToken() == "fstsw" || Op->getToken() == "fstsww" || + Op->getToken() == "fstcw" || Op->getToken() == "fstcww" || Op->getToken() == "finit" || Op->getToken() == "fsave" || - Op->getToken() == "fstenv") { + Op->getToken() == "fstenv" || Op->getToken() == "fclex") { MCInst Inst; Inst.setOpcode(X86::WAIT); Out.EmitInstruction(Inst); @@ -1187,8 +1189,11 @@ MatchAndEmitInstruction(SMLoc IDLoc, .Case("finit", "fninit") .Case("fsave", "fnsave") .Case("fstcw", "fnstcw") + .Case("fstcww", "fnstcw") .Case("fstenv", "fnstenv") .Case("fstsw", "fnstsw") + .Case("fstsww", "fnstsw") + .Case("fclex", "fnclex") .Default(0); assert(Repl && "Unknown wait-prefixed instruction"); delete Operands[0]; diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td index 0087e4892b..57634d3c0f 100644 --- a/lib/Target/X86/X86InstrFPStack.td +++ b/lib/Target/X86/X86InstrFPStack.td @@ -340,7 +340,7 @@ def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">; def FRSTORm : FPI<0xDD, MRM4m, (outs f32mem:$dst), (ins), "frstor\t$dst">; def FSAVEm : FPI<0xDD, MRM6m, (outs f32mem:$dst), (ins), "fnsave\t$dst">; -def FNSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fnstsw\t$dst">; +def FNSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fnstsw{w}\t$dst">; def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">; def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">; @@ -600,12 +600,12 @@ def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags (outs), (ins), "fnstsw %ax", []>, DF; def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world - (outs), (ins i16mem:$dst), "fnstcw\t$dst", + (outs), (ins i16mem:$dst), "fnstcw{w}\t$dst", [(X86fp_cwd_get16 addr:$dst)]>; let mayLoad = 1 in def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] - (outs), (ins i16mem:$dst), "fldcw\t$dst", []>; + (outs), (ins i16mem:$dst), "fldcw{w}\t$dst", []>; // FPU control instructions def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB; diff --git a/lib/Target/X86/X86InstrSystem.td b/lib/Target/X86/X86InstrSystem.td index 48b6d6ecf0..835794d5d4 100644 --- a/lib/Target/X86/X86InstrSystem.td +++ b/lib/Target/X86/X86InstrSystem.td @@ -310,13 +310,13 @@ def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src), def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), - "verr\t$seg", []>, TB; + "verr{w}\t$seg", []>, TB; def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), - "verr\t$seg", []>, TB; + "verr{w}\t$seg", []>, TB; def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), - "verw\t$seg", []>, TB; + "verw{w}\t$seg", []>, TB; def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), - "verw\t$seg", []>, TB; + "verw{w}\t$seg", []>, TB; //===----------------------------------------------------------------------===// // Descriptor-table support instructions |