diff options
Diffstat (limited to 'lib')
67 files changed, 482 insertions, 484 deletions
diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index ef1fca0ea3..801bd1b1fa 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -1179,11 +1179,11 @@ void AsmPrinter::printInlineAsm(const MachineInstr *MI) const { // Count the number of register definitions. unsigned NumDefs = 0; - for (; MI->getOperand(NumDefs).isRegister() && MI->getOperand(NumDefs).isDef(); + for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef(); ++NumDefs) assert(NumDefs != NumOperands-1 && "No asm string?"); - assert(MI->getOperand(NumDefs).isExternalSymbol() && "No asm string?"); + assert(MI->getOperand(NumDefs).isSymbol() && "No asm string?"); // Disassemble the AsmStr, printing out the literal pieces, the operands, etc. const char *AsmStr = MI->getOperand(NumDefs).getSymbolName(); diff --git a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp index 06282211d1..168b36c244 100644 --- a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp +++ b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp @@ -1050,15 +1050,15 @@ public: } // If advancing cfa. - if (Dst.isRegister() && Dst.getRegister() == MachineLocation::VirtualFP) { - if (!Src.isRegister()) { - if (Src.getRegister() == MachineLocation::VirtualFP) { + if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) { + if (!Src.isReg()) { + if (Src.getReg() == MachineLocation::VirtualFP) { Asm->EmitInt8(DW_CFA_def_cfa_offset); Asm->EOL("DW_CFA_def_cfa_offset"); } else { Asm->EmitInt8(DW_CFA_def_cfa); Asm->EOL("DW_CFA_def_cfa"); - Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister(), isEH)); + Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Src.getReg(), isEH)); Asm->EOL("Register"); } @@ -1069,18 +1069,18 @@ public: } else { assert(0 && "Machine move no supported yet."); } - } else if (Src.isRegister() && - Src.getRegister() == MachineLocation::VirtualFP) { - if (Dst.isRegister()) { + } else if (Src.isReg() && + Src.getReg() == MachineLocation::VirtualFP) { + if (Dst.isReg()) { Asm->EmitInt8(DW_CFA_def_cfa_register); Asm->EOL("DW_CFA_def_cfa_register"); - Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getRegister(), isEH)); + Asm->EmitULEB128Bytes(RI->getDwarfRegNum(Dst.getReg(), isEH)); Asm->EOL("Register"); } else { assert(0 && "Machine move no supported yet."); } } else { - unsigned Reg = RI->getDwarfRegNum(Src.getRegister(), isEH); + unsigned Reg = RI->getDwarfRegNum(Src.getReg(), isEH); int Offset = Dst.getOffset() / stackGrowth; if (Offset < 0) { @@ -1409,10 +1409,10 @@ private: /// provided. void AddAddress(DIE *Die, unsigned Attribute, const MachineLocation &Location) { - unsigned Reg = RI->getDwarfRegNum(Location.getRegister(), false); + unsigned Reg = RI->getDwarfRegNum(Location.getReg(), false); DIEBlock *Block = new DIEBlock(); - if (Location.isRegister()) { + if (Location.isReg()) { if (Reg < 32) { AddUInt(Block, 0, DW_FORM_data1, DW_OP_reg0 + Reg); } else { diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp index 882826534d..3b30423c52 100644 --- a/lib/CodeGen/BranchFolding.cpp +++ b/lib/CodeGen/BranchFolding.cpp @@ -161,7 +161,7 @@ bool BranchFolder::OptimizeImpDefsBlock(MachineBasicBlock *MBB) { // See if it uses any of the implicitly defined registers. for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { MachineOperand &MO = I->getOperand(i); - if (!MO.isRegister() || !MO.isUse()) + if (!MO.isReg() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); if (ImpDefRegs.count(Reg)) @@ -235,7 +235,7 @@ bool BranchFolder::runOnMachineFunction(MachineFunction &MF) { I != E; ++I) for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) { MachineOperand &Op = I->getOperand(op); - if (!Op.isJumpTableIndex()) continue; + if (!Op.isJTI()) continue; unsigned NewIdx = JTMapping[Op.getIndex()]; Op.setIndex(NewIdx); diff --git a/lib/CodeGen/DeadMachineInstructionElim.cpp b/lib/CodeGen/DeadMachineInstructionElim.cpp index 718b6e2a5a..305ec0e798 100644 --- a/lib/CodeGen/DeadMachineInstructionElim.cpp +++ b/lib/CodeGen/DeadMachineInstructionElim.cpp @@ -58,7 +58,7 @@ bool DeadMachineInstructionElim::isDead(MachineInstr *MI) const { // Examine each operand. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDef()) { + if (MO.isReg() && MO.isDef()) { unsigned Reg = MO.getReg(); if (TargetRegisterInfo::isPhysicalRegister(Reg) ? LivePhysRegs[Reg] : !MRI->use_empty(Reg)) { @@ -122,7 +122,7 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) { // Record the physreg defs. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isDef()) { + if (MO.isReg() && MO.isDef()) { unsigned Reg = MO.getReg(); if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) { LivePhysRegs.reset(Reg); @@ -136,7 +136,7 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) { // both defined and used in the same instruction. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isUse()) { + if (MO.isReg() && MO.isUse()) { unsigned Reg = MO.getReg(); if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) { LivePhysRegs.set(Reg); diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index c95279ebf2..98ff22ce6e 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -302,7 +302,7 @@ bool LiveIntervals::conflictsWithPhysRegDef(const LiveInterval &li, continue; for (unsigned i = 0; i != MI->getNumOperands(); ++i) { MachineOperand& mop = MI->getOperand(i); - if (!mop.isRegister()) + if (!mop.isReg()) continue; unsigned PhysReg = mop.getReg(); if (PhysReg == 0 || PhysReg == li.reg) @@ -723,7 +723,7 @@ void LiveIntervals::computeIntervals() { for (int i = MI->getNumOperands() - 1; i >= 0; --i) { MachineOperand &MO = MI->getOperand(i); // handle register defs - build intervals - if (MO.isRegister() && MO.getReg() && MO.isDef()) { + if (MO.isReg() && MO.getReg() && MO.isDef()) { handleRegisterDef(MBB, MI, MIIndex, MO, i); } } @@ -789,7 +789,7 @@ unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li, unsigned RegOp = 0; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister() || !MO.isUse()) + if (!MO.isReg() || !MO.isUse()) continue; unsigned Reg = MO.getReg(); if (Reg == 0 || Reg == li.reg) @@ -876,7 +876,7 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li, unsigned ImpUse = 0; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister()) { + if (MO.isReg()) { unsigned Reg = MO.getReg(); if (Reg == 0) continue; @@ -1093,7 +1093,7 @@ void LiveIntervals::rewriteImplicitOps(const LiveInterval &li, // use operand. Make sure we rewrite that as well. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (!MO.isRegister()) + if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); if (Reg == 0 || TargetRegisterInfo::isPhysicalRegister(Reg)) @@ -1128,7 +1128,7 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, RestartInstruction: for (unsigned i = 0; i != MI->getNumOperands(); ++i) { MachineOperand& mop = MI->getOperand(i); - if (!mop.isRegister()) + if (!mop.isReg()) continue; unsigned Reg = mop.getReg(); unsigned RegI = Reg; @@ -1180,7 +1180,7 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI, Ops.push_back(i); for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) { const MachineOperand &MOj = MI->getOperand(j); - if (!MOj.isRegister()) + if (!MOj.isReg()) continue; unsigned RegJ = MOj.getReg(); if (RegJ == 0 || TargetRegisterInfo::isPhysicalRegister(RegJ)) @@ -1618,7 +1618,7 @@ LiveIntervals::handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm, NewLIs.push_back(&getOrCreateInterval(NewVReg)); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.getReg() == li.reg) + if (MO.isReg() && MO.getReg() == li.reg) MO.setReg(NewVReg); } } @@ -1662,7 +1662,7 @@ addIntervalsForSpillsFast(const LiveInterval &li, for (unsigned i = 0; i != MI->getNumOperands(); ++i) { MachineOperand& mop = MI->getOperand(i); - if (!mop.isRegister() || mop.getReg() != li.reg) continue; + if (!mop.isReg() || mop.getReg() != li.reg) continue; HasUse |= MI->getOperand(i).isUse(); HasDef |= MI->getOperand(i).isDef(); @@ -1916,7 +1916,7 @@ addIntervalsForSpills(const LiveInterval &li, CanFold = true; for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) { MachineOperand &MO = MI->getOperand(j); - if (!MO.isRegister() || MO.getReg() != VReg) + if (!MO.isReg() || MO.getReg() != VReg) continue; Ops.push_back(j); @@ -1987,7 +1987,7 @@ addIntervalsForSpills(const LiveInterval &li, CanFold = true; for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) { MachineOperand &MO = MI->getOperand(j); - if (!MO.isRegister() || MO.getReg() != VReg) + if (!MO.isReg() || MO.getReg() != VReg) continue; if (MO.isDef()) { diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp index 7c4b77f41b..632cd8210a 100644 --- a/lib/CodeGen/LiveVariables.cpp +++ b/lib/CodeGen/LiveVariables.cpp @@ -558,7 +558,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { SmallVector<unsigned, 4> DefRegs; for (unsigned i = 0; i != NumOperandsToProcess; ++i) { const MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.getReg()) { + if (MO.isReg() && MO.getReg()) { unsigned MOReg = MO.getReg(); if (MO.isUse()) UseRegs.push_back(MOReg); @@ -672,7 +672,7 @@ void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI, void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); - if (MO.isRegister() && MO.isKill()) { + if (MO.isReg() && MO.isKill()) { MO.setIsKill(false); unsigned Reg = MO.getReg(); if (TargetRegisterInfo::isVirtualRegister(Reg)) { diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp index f9cef4ccfb..6ee955d379 100644 --- a/lib/CodeGen/LowerSubregs.cpp +++ b/lib/CodeGen/LowerSubregs.cpp @@ -64,9 +64,9 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() && - MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() && - MI->getOperand(2).isImmediate() && "Malformed extract_subreg"); + assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && + MI->getOperand(1).isReg() && MI->getOperand(1).isUse() && + MI->getOperand(2).isImm() && "Malformed extract_subreg"); unsigned DstReg = MI->getOperand(0).getReg(); unsigned SuperReg = MI->getOperand(1).getReg(); @@ -102,10 +102,10 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) { MachineFunction &MF = *MBB->getParent(); const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) && - MI->getOperand(1).isImmediate() && - (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) && - MI->getOperand(3).isImmediate() && "Invalid subreg_to_reg"); + assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && + MI->getOperand(1).isImm() && + (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && + MI->getOperand(3).isImm() && "Invalid subreg_to_reg"); unsigned DstReg = MI->getOperand(0).getReg(); unsigned InsReg = MI->getOperand(2).getReg(); @@ -146,10 +146,10 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { MachineFunction &MF = *MBB->getParent(); const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) && - (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) && - (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) && - MI->getOperand(3).isImmediate() && "Invalid insert_subreg"); + assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && + (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) && + (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && + MI->getOperand(3).isImm() && "Invalid insert_subreg"); unsigned DstReg = MI->getOperand(0).getReg(); unsigned SrcReg = MI->getOperand(1).getReg(); diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp index bac0a6cc71..db55a88edd 100644 --- a/lib/CodeGen/MachineBasicBlock.cpp +++ b/lib/CodeGen/MachineBasicBlock.cpp @@ -290,7 +290,7 @@ void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old, // Scan the operands of this machine instruction, replacing any uses of Old // with New. for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) - if (I->getOperand(i).isMachineBasicBlock() && + if (I->getOperand(i).isMBB() && I->getOperand(i).getMBB() == Old) I->getOperand(i).setMBB(New); } diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 4a7059a515..5a617e8127 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -37,7 +37,7 @@ using namespace llvm; /// MachineRegisterInfo. If it is null, then the next/prev fields should be /// explicitly nulled out. void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { - assert(isRegister() && "Can only add reg operand to use lists"); + assert(isReg() && "Can only add reg operand to use lists"); // If the reginfo pointer is null, just explicitly null out or next/prev // pointers, to ensure they are not garbage. @@ -92,7 +92,7 @@ void MachineOperand::setReg(unsigned Reg) { void MachineOperand::ChangeToImmediate(int64_t ImmVal) { // If this operand is currently a register operand, and if this is in a |