diff options
Diffstat (limited to 'lib')
61 files changed, 276 insertions, 314 deletions
diff --git a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index cc1581b53b..f1a45fd7ee 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -42,8 +42,8 @@ AsmVerbose("asm-verbose", cl::desc("Add comments to directives."), char AsmPrinter::ID = 0; AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm, - const TargetAsmInfo *T, unsigned OL, bool VDef) - : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o), + const TargetAsmInfo *T, bool F, bool VDef) + : MachineFunctionPass(&ID), FunctionNumber(0), Fast(F), O(o), TM(tm), TAI(T), TRI(tm.getRegisterInfo()), IsInTextSection(false) { diff --git a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp index 9f74b6ab9d..73326135a6 100644 --- a/lib/CodeGen/AsmPrinter/DwarfWriter.cpp +++ b/lib/CodeGen/AsmPrinter/DwarfWriter.cpp @@ -3351,7 +3351,7 @@ public: } /// ValidDebugInfo - Return true if V represents valid debug info value. - bool ValidDebugInfo(Value *V, unsigned OptLevel) { + bool ValidDebugInfo(Value *V, bool FastISel) { if (!V) return false; @@ -3393,7 +3393,7 @@ public: case DW_TAG_lexical_block: /// FIXME. This interfers with the qualitfy of generated code when /// during optimization. - if (OptLevel != 0) + if (FastISel == false) return false; default: break; @@ -3574,6 +3574,7 @@ public: return 0; SmallVector<DbgScope *, 2> &Scopes = I->second; + if (Scopes.empty()) return 0; DbgScope *Scope = Scopes.back(); Scopes.pop_back(); unsigned ID = MMI->NextLabelID(); MMI->RecordUsedDbgLabel(ID); @@ -4730,8 +4731,8 @@ void DwarfWriter::EndFunction(MachineFunction *MF) { } /// ValidDebugInfo - Return true if V represents valid debug info value. -bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) { - return DD && DD->ValidDebugInfo(V, OptLevel); +bool DwarfWriter::ValidDebugInfo(Value *V, bool FastISel) { + return DD && DD->ValidDebugInfo(V, FastISel); } /// RecordSourceLine - Records location information and associates it with a diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index 92aeb64c7d..086104912b 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -55,9 +55,9 @@ FileModel::Model LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, raw_ostream &Out, CodeGenFileType FileType, - unsigned OptLevel) { + bool Fast) { // Add common CodeGen passes. - if (addCommonCodeGenPasses(PM, OptLevel)) + if (addCommonCodeGenPasses(PM, Fast)) return FileModel::Error; // Fold redundant debug labels. @@ -66,17 +66,17 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (addPreEmitPass(PM, OptLevel) && PrintMachineCode) + if (addPreEmitPass(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (OptLevel != 0) + if (!Fast) PM.add(createLoopAlignerPass()); switch (FileType) { default: break; case TargetMachine::AssemblyFile: - if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out)) + if (addAssemblyEmitter(PM, Fast, getAsmVerbosityDefault(), Out)) return FileModel::Error; return FileModel::AsmFile; case TargetMachine::ObjectFile: @@ -94,9 +94,9 @@ LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, /// finish up adding passes to emit the file, if necessary. bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM, MachineCodeEmitter *MCE, - unsigned OptLevel) { + bool Fast) { if (MCE) - addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE); + addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE); PM.add(createGCInfoDeleter()); @@ -114,15 +114,15 @@ bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM, /// bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM, MachineCodeEmitter &MCE, - unsigned OptLevel) { + bool Fast) { // Add common CodeGen passes. - if (addCommonCodeGenPasses(PM, OptLevel)) + if (addCommonCodeGenPasses(PM, Fast)) return true; - if (addPreEmitPass(PM, OptLevel) && PrintMachineCode) + if (addPreEmitPass(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE); + addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE); PM.add(createGCInfoDeleter()); @@ -135,12 +135,11 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM, /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for /// both emitting to assembly files or machine code output. /// -bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, - unsigned OptLevel) { +bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) { // Standard LLVM-Level Passes. // Run loop strength reduction before anything else. - if (OptLevel != 0) { + if (!Fast) { PM.add(createLoopStrengthReducePass(getTargetLowering())); if (PrintLSR) PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs())); @@ -154,7 +153,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, // Make sure that no unreachable blocks are instruction selected. PM.add(createUnreachableBlockEliminationPass()); - if (OptLevel != 0) + if (!Fast) PM.add(createCodeGenPreparePass(getTargetLowering())); PM.add(createStackProtectorPass(getTargetLowering())); @@ -168,38 +167,38 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, // Enable FastISel with -fast, but allow that to be overridden. if (EnableFastISelOption == cl::BOU_TRUE || - (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE)) + (Fast && EnableFastISelOption != cl::BOU_FALSE)) EnableFastISel = true; // Ask the target for an isel. - if (addInstSelector(PM, OptLevel)) + if (addInstSelector(PM, Fast)) return true; // Print the instruction selected machine code... if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (OptLevel != 0) { + if (!Fast) { PM.add(createMachineLICMPass()); PM.add(createMachineSinkingPass()); } // Run pre-ra passes. - if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode) + if (addPreRegAlloc(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); // Perform register allocation. PM.add(createRegisterAllocator()); // Perform stack slot coloring. - if (OptLevel != 0) + if (!Fast) PM.add(createStackSlotColoringPass()); if (PrintMachineCode) // Print the register-allocated code PM.add(createMachineFunctionPrinterPass(cerr)); // Run post-ra passes. - if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode) + if (addPostRegAlloc(PM, Fast) && PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); if (PrintMachineCode) @@ -217,7 +216,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, PM.add(createMachineFunctionPrinterPass(cerr)); // Second pass scheduler. - if (OptLevel != 0 && !DisablePostRAScheduler) { + if (!Fast && !DisablePostRAScheduler) { PM.add(createPostRAScheduler()); if (PrintMachineCode) @@ -225,7 +224,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, } // Branch folding must be run after regalloc and prolog/epilog insertion. - if (OptLevel != 0) + if (!Fast) PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); if (PrintMachineCode) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8a41423cbe..bd724afa54 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -57,9 +57,9 @@ namespace { SelectionDAG &DAG; const TargetLowering &TLI; CombineLevel Level; - unsigned OptLevel; bool LegalOperations; bool LegalTypes; + bool Fast; // Worklist of all of the nodes that need to be simplified. std::vector<SDNode*> WorkList; @@ -254,13 +254,13 @@ namespace { } public: - DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL) + DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), - OptLevel(OL), LegalOperations(false), LegalTypes(false), + Fast(fast), AA(A) {} /// Run - runs the dag combiner on all nodes in the work list @@ -4784,7 +4784,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) { SDValue Ptr = LD->getBasePtr(); // Try to infer better alignment information than the load already has. - if (OptLevel != 0 && LD->isUnindexed()) { + if (!Fast && LD->isUnindexed()) { if (unsigned Align = InferAlignment(Ptr, DAG)) { if (Align > LD->getAlignment()) return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), @@ -4904,7 +4904,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { SDValue Ptr = ST->getBasePtr(); // Try to infer better alignment information than the store already has. - if (OptLevel != 0 && ST->isUnindexed()) { + if (!Fast && ST->isUnindexed()) { if (unsigned Align = InferAlignment(Ptr, DAG)) { if (Align > ST->getAlignment()) return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, @@ -6084,9 +6084,8 @@ SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { // SelectionDAG::Combine - This is the entry point for the file. // -void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, - unsigned OptLevel) { +void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) { /// run - This is the main entry point to this class. /// - DAGCombiner(*this, AA, OptLevel).Run(Level); + DAGCombiner(*this, AA, Fast).Run(Level); } diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index a7801ebccf..12b0b12c40 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -327,7 +327,7 @@ bool FastISel::SelectCall(User *I) { default: break; case Intrinsic::dbg_stoppoint: { DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); - if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) { + if (DW && DW->ValidDebugInfo(SPI->getContext(), true)) { DICompileUnit CU(cast<GlobalVariable>(SPI->getContext())); std::string Dir, FN; unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir), @@ -344,7 +344,7 @@ bool FastISel::SelectCall(User *I) { } case Intrinsic::dbg_region_start: { DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I); - if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) { + if (DW && DW->ValidDebugInfo(RSI->getContext(), true)) { unsigned ID = DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext())); const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); @@ -354,7 +354,7 @@ bool FastISel::SelectCall(User *I) { } case Intrinsic::dbg_region_end: { DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I); - if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) { + if (DW && DW->ValidDebugInfo(REI->getContext(), true)) { unsigned ID = 0; DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext())); if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) { @@ -380,7 +380,7 @@ bool FastISel::SelectCall(User *I) { DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); Value *SP = FSI->getSubprogram(); - if (DW->ValidDebugInfo(SP, 0)) { + if (DW->ValidDebugInfo(SP, true)) { // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what // (most?) gdb expects. DebugLoc PrevLoc = DL; @@ -425,7 +425,7 @@ bool FastISel::SelectCall(User *I) { case Intrinsic::dbg_declare: { DbgDeclareInst *DI = cast<DbgDeclareInst>(I); Value *Variable = DI->getVariable(); - if (DW && DW->ValidDebugInfo(Variable, 0)) { + if (DW && DW->ValidDebugInfo(Variable, true)) { // Determine the address of the declared object. Value *Address = DI->getAddress(); if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 25305ea243..0b019fdeee 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -55,8 +55,8 @@ namespace { class VISIBILITY_HIDDEN SelectionDAGLegalize { TargetLowering &TLI; SelectionDAG &DAG; - unsigned OptLevel; bool TypesNeedLegalizing; + bool Fast; // Libcall insertion helpers. @@ -139,7 +139,7 @@ class VISIBILITY_HIDDEN SelectionDAGLegalize { public: explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing, - unsigned ol); + bool fast); /// getTypeAction - Return how we should legalize values of this type, either /// it is already legal or we need to expand it into multiple registers of @@ -345,9 +345,9 @@ SDValue SelectionDAGLegalize::promoteShuffle(MVT NVT, MVT VT, DebugLoc dl, } SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, - bool types, unsigned ol) - : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), - TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) { + bool types, bool fast) + : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types), + Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) { assert(MVT::LAST_VALUETYPE <= 32 && "Too many value types for ValueTypeActions to hold!"); } @@ -1271,7 +1271,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { unsigned Line = DSP->getLine(); unsigned Col = DSP->getColumn(); - if (OptLevel == 0) { + if (Fast) { // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it // won't hurt anything. if (useDEBUG_LOC) { @@ -8566,9 +8566,9 @@ SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST, // SelectionDAG::Legalize - This is the entry point for the file. // -void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned OptLevel) { +void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) { /// run - This is the main entry point to this class. /// - SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG(); + SelectionDAGLegalize(*this, TypesNeedLegalizing, Fast).LegalizeDAG(); } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp index c87820a97b..0c343f9880 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -630,6 +630,6 @@ void ScheduleDAGFast::ListScheduleBottomUp() { //===----------------------------------------------------------------------===// llvm::ScheduleDAGSDNodes * -llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) { +llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) { return new ScheduleDAGFast(*IS->MF); } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index 2ac934a0d0..e63484e987 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -261,7 +261,7 @@ void ScheduleDAGList::ListScheduleTopDown() { /// new hazard recognizer. This scheduler takes ownership of the hazard /// recognizer and deletes it when done. ScheduleDAGSDNodes * -llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) { +llvm::createTDListDAGScheduler(SelectionDAGISel *IS, bool Fast) { return new ScheduleDAGList(*IS->MF, new LatencyPriorityQueue(), IS->CreateTargetHazardRecognizer()); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index aecd02aba3..20a081d054 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1505,7 +1505,7 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const { //===----------------------------------------------------------------------===// llvm::ScheduleDAGSDNodes * -llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) { +llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, bool) { const TargetMachine &TM = IS->TM; const TargetInstrInfo *TII = TM.g |