diff options
Diffstat (limited to 'lib')
40 files changed, 331 insertions, 372 deletions
diff --git a/lib/Analysis/IPA/FindUnsafePointerTypes.cpp b/lib/Analysis/IPA/FindUnsafePointerTypes.cpp index d689d93cd4..9f908c6c71 100644 --- a/lib/Analysis/IPA/FindUnsafePointerTypes.cpp +++ b/lib/Analysis/IPA/FindUnsafePointerTypes.cpp @@ -95,11 +95,3 @@ void FindUnsafePointerTypes::printResults(const Module *M, CW << " #" << Counter << ". " << (Value*)*I << "\n"; } } - -// getAnalysisUsageInfo - Of course, we provide ourself... -// -void FindUnsafePointerTypes::getAnalysisUsageInfo(Pass::AnalysisSet &Required, - Pass::AnalysisSet &Destroyed, - Pass::AnalysisSet &Provided) { - Provided.push_back(FindUnsafePointerTypes::ID); -} diff --git a/lib/Analysis/IPA/FindUsedTypes.cpp b/lib/Analysis/IPA/FindUsedTypes.cpp index 5c961d2beb..86061d8610 100644 --- a/lib/Analysis/IPA/FindUsedTypes.cpp +++ b/lib/Analysis/IPA/FindUsedTypes.cpp @@ -93,11 +93,3 @@ void FindUsedTypes::printTypes(std::ostream &o, const Module *M = 0) const { E = UsedTypes.end(); I != E; ++I) o << " " << *I << "\n"; } - -// getAnalysisUsageInfo - Of course, we provide ourself... -// -void FindUsedTypes::getAnalysisUsageInfo(Pass::AnalysisSet &Required, - Pass::AnalysisSet &Destroyed, - Pass::AnalysisSet &Provided) { - Provided.push_back(FindUsedTypes::ID); -} diff --git a/lib/Analysis/IntervalPartition.cpp b/lib/Analysis/IntervalPartition.cpp index 197bed26d7..bb0f582108 100644 --- a/lib/Analysis/IntervalPartition.cpp +++ b/lib/Analysis/IntervalPartition.cpp @@ -52,19 +52,19 @@ void IntervalPartition::updatePredecessors(cfg::Interval *Int) { // IntervalPartition ctor - Build the first level interval partition for the // specified function... // -bool IntervalPartition::runOnMethod(Function *M) { - assert(M->front() && "Cannot operate on prototypes!"); +bool IntervalPartition::runOnFunction(Function *F) { + assert(F->front() && "Cannot operate on prototypes!"); // Pass false to intervals_begin because we take ownership of it's memory - function_interval_iterator I = intervals_begin(M, false); - assert(I != intervals_end(M) && "No intervals in function!?!?!"); + function_interval_iterator I = intervals_begin(F, false); + assert(I != intervals_end(F) && "No intervals in function!?!?!"); addIntervalToPartition(RootInterval = *I); ++I; // After the first one... // Add the rest of the intervals to the partition... - for_each(I, intervals_end(M), + for_each(I, intervals_end(F), bind_obj(this, &IntervalPartition::addIntervalToPartition)); // Now that we know all of the successor information, propogate this to the diff --git a/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp b/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp index e9e4245cca..0518aef3b8 100644 --- a/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp +++ b/lib/Analysis/LiveVar/FunctionLiveVarInfo.cpp @@ -1,6 +1,6 @@ -//===-- MethodLiveVarInfo.cpp - Live Variable Analysis for a Function -----===// +//===-- FunctionLiveVarInfo.cpp - Live Variable Analysis for a Function ---===// // -// This is the interface to method level live variable information that is +// This is the interface to function level live variable information that is // provided by live variable analysis. // //===----------------------------------------------------------------------===// @@ -39,10 +39,10 @@ const ValueSet &MethodLiveVarInfo::getInSetOfBB(const BasicBlock *BB) const { //----------------------------------------------------------------------------- -// Performs live var analysis for a method +// Performs live var analysis for a function //----------------------------------------------------------------------------- -bool MethodLiveVarInfo::runOnMethod(Function *Meth) { +bool MethodLiveVarInfo::runOnFunction(Function *Meth) { M = Meth; if (DEBUG_LV) std::cerr << "Analysing live variables ...\n"; @@ -149,12 +149,12 @@ void MethodLiveVarInfo::releaseMemory() { //----------------------------------------------------------------------------- // Following functions will give the LiveVar info for any machine instr in -// a method. It should be called after a call to analyze(). +// a function. It should be called after a call to analyze(). // // Thsese functions calucluates live var info for all the machine instrs in a // BB when LVInfo for one inst is requested. Hence, this function is useful // when live var info is required for many (or all) instructions in a basic -// block. Also, the arguments to this method does not require specific +// block. Also, the arguments to this function does not require specific // iterators. //----------------------------------------------------------------------------- diff --git a/lib/Analysis/LoopInfo.cpp b/lib/Analysis/LoopInfo.cpp index ef47936bba..c34aef7b9c 100644 --- a/lib/Analysis/LoopInfo.cpp +++ b/lib/Analysis/LoopInfo.cpp @@ -35,7 +35,7 @@ void cfg::LoopInfo::releaseMemory() { //===----------------------------------------------------------------------===// // cfg::LoopInfo implementation // -bool cfg::LoopInfo::runOnMethod(Function *F) { +bool cfg::LoopInfo::runOnFunction(Function *F) { releaseMemory(); Calculate(getAnalysis<DominatorSet>()); // Update return false; @@ -53,11 +53,10 @@ void cfg::LoopInfo::Calculate(const DominatorSet &DS) { TopLevelLoops[i]->setLoopDepth(1); } -void cfg::LoopInfo::getAnalysisUsageInfo(Pass::AnalysisSet &Required, - Pass::AnalysisSet &Destroyed, - Pass::AnalysisSet &Provided) { - Required.push_back(DominatorSet::ID); - Provided.push_back(ID); +void cfg::LoopInfo::getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesAll(); + AU.addRequired(DominatorSet::ID); + AU.addProvided(ID); } diff --git a/lib/Analysis/PostDominators.cpp b/lib/Analysis/PostDominators.cpp index 71ee3d74cf..387b673f60 100644 --- a/lib/Analysis/PostDominators.cpp +++ b/lib/Analysis/PostDominators.cpp @@ -22,7 +22,7 @@ using std::set; AnalysisID cfg::DominatorSet::ID(AnalysisID::create<cfg::DominatorSet>()); AnalysisID cfg::DominatorSet::PostDomID(AnalysisID::create<cfg::DominatorSet>()); -bool cfg::DominatorSet::runOnMethod(Function *F) { +bool cfg::DominatorSet::runOnFunction(Function *F) { Doms.clear(); // Reset from the last time we were run... if (isPostDominator()) @@ -129,17 +129,16 @@ void cfg::DominatorSet::calcPostDominatorSet(Function *M) { } while (Changed); } -// getAnalysisUsageInfo - This obviously provides a dominator set, but it also -// uses the UnifyMethodExitNodes pass if building post-dominators +// getAnalysisUsage - This obviously provides a dominator set, but it also +// uses the UnifyFunctionExitNodes pass if building post-dominators // -void cfg::DominatorSet::getAnalysisUsageInfo(Pass::AnalysisSet &Requires, - Pass::AnalysisSet &Destroyed, - Pass::AnalysisSet &Provided) { +void cfg::DominatorSet::getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesAll(); if (isPostDominator()) { - Provided.push_back(PostDomID); - Requires.push_back(UnifyMethodExitNodes::ID); + AU.addProvided(PostDomID); + AU.addRequired(UnifyMethodExitNodes::ID); } else { - Provided.push_back(ID); + AU.addProvided(ID); } } diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp index f10bf3c412..adc8903541 100644 --- a/lib/CodeGen/InstrSched/InstrScheduling.cpp +++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp @@ -1480,26 +1480,23 @@ instrIsFeasible(const SchedulingManager& S, //--------------------------------------------------------------------------- namespace { - class InstructionSchedulingWithSSA : public MethodPass { + class InstructionSchedulingWithSSA : public FunctionPass { const TargetMachine ⌖ public: inline InstructionSchedulingWithSSA(const TargetMachine &T) : target(T) {} - // getAnalysisUsageInfo - We use LiveVarInfo... - virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires, - Pass::AnalysisSet &Destroyed, - Pass::AnalysisSet &Provided) { - Requires.push_back(MethodLiveVarInfo::ID); - Destroyed.push_back(MethodLiveVarInfo::ID); + // getAnalysisUsage - We use LiveVarInfo... + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(MethodLiveVarInfo::ID); } - bool runOnMethod(Function *F); + bool runOnFunction(Function *F); }; } // end anonymous namespace bool -InstructionSchedulingWithSSA::runOnMethod(Function *M) +InstructionSchedulingWithSSA::runOnFunction(Function *M) { if (SchedDebugLevel == Sched_Disable) return false; @@ -1544,8 +1541,6 @@ InstructionSchedulingWithSSA::runOnMethod(Function *M) } -MethodPass* -createInstructionSchedulingWithSSAPass(const TargetMachine &tgt) -{ +Pass *createInstructionSchedulingWithSSAPass(const TargetMachine &tgt) { return new InstructionSchedulingWithSSA(tgt); } diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp index 0b680ab9e4..c22ede96b3 100644 --- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp +++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp @@ -40,14 +40,14 @@ cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags, // RegisterAllocation pass front end... //---------------------------------------------------------------------------- namespace { - class RegisterAllocator : public MethodPass { + class RegisterAllocator : public FunctionPass { TargetMachine &Target; public: inline RegisterAllocator(TargetMachine &T) : Target(T) {} - bool runOnMethod(Function *F) { + bool runOnFunction(Function *F) { if (DEBUG_RA) - cerr << "\n******************** Method "<< F->getName() + cerr << "\n******************** Function "<< F->getName() << " ********************\n"; PhyRegAlloc PRA(F, Target, &getAnalysis<MethodLiveVarInfo>(), @@ -58,17 +58,14 @@ namespace { return false; } - virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires, - Pass::AnalysisSet &Destroyed, - Pass::AnalysisSet &Provided) { - Requires.push_back(cfg::LoopInfo::ID); - Requires.push_back(MethodLiveVarInfo::ID); - Destroyed.push_back(MethodLiveVarInfo::ID); + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(cfg::LoopInfo::ID); + AU.addRequired(MethodLiveVarInfo::ID); } }; } -MethodPass *getRegisterAllocator(TargetMachine &T) { +Pass *getRegisterAllocator(TargetMachine &T) { return new RegisterAllocator(T); } diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp index f10bf3c412..adc8903541 100644 --- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp +++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp @@ -1480,26 +1480,23 @@ instrIsFeasible(const SchedulingManager& S, //--------------------------------------------------------------------------- namespace { - class InstructionSchedulingWithSSA : public MethodPass { + class InstructionSchedulingWithSSA : public FunctionPass { const TargetMachine ⌖ public: inline InstructionSchedulingWithSSA(const TargetMachine &T) : target(T) {} - // getAnalysisUsageInfo - We use LiveVarInfo... - virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires, - Pass::AnalysisSet &Destroyed, - Pass::AnalysisSet &Provided) { - Requires.push_back(MethodLiveVarInfo::ID); - Destroyed.push_back(MethodLiveVarInfo::ID); + // getAnalysisUsage - We use LiveVarInfo... + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(MethodLiveVarInfo::ID); } - bool runOnMethod(Function *F); + bool runOnFunction(Function *F); }; } // end anonymous namespace bool -InstructionSchedulingWithSSA::runOnMethod(Function *M) +InstructionSchedulingWithSSA::runOnFunction(Function *M) { if (SchedDebugLevel == Sched_Disable) return false; @@ -1544,8 +1541,6 @@ InstructionSchedulingWithSSA::runOnMethod(Function *M) } -MethodPass* -createInstructionSchedulingWithSSAPass(const TargetMachine &tgt) -{ +Pass *createInstructionSchedulingWithSSAPass(const TargetMachine &tgt) { return new InstructionSchedulingWithSSA(tgt); } diff --git a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp index e9e4245cca..0518aef3b8 100644 --- a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp +++ b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp @@ -1,6 +1,6 @@ -//===-- MethodLiveVarInfo.cpp - Live Variable Analysis for a Function -----===// +//===-- FunctionLiveVarInfo.cpp - Live Variable Analysis for a Function ---===// // -// This is the interface to method level live variable information that is +// This is the interface to function level live variable information that is // provided by live variable analysis. // //===----------------------------------------------------------------------===// @@ -39,10 +39,10 @@ const ValueSet &MethodLiveVarInfo::getInSetOfBB(const BasicBlock *BB) const { //----------------------------------------------------------------------------- -// Performs live var analysis for a method +// Performs live var analysis for a function //----------------------------------------------------------------------------- -bool MethodLiveVarInfo::runOnMethod(Function *Meth) { +bool MethodLiveVarInfo::runOnFunction(Function *Meth) { M = Meth; if (DEBUG_LV) std::cerr << "Analysing live variables ...\n"; @@ -149,12 +149,12 @@ void MethodLiveVarInfo::releaseMemory() { //----------------------------------------------------------------------------- // Following functions will give the LiveVar info for any machine instr in -// a method. It should be called after a call to analyze(). +// a function. It should be called after a call to analyze(). // // Thsese functions calucluates live var info for all the machine instrs in a // BB when LVInfo for one inst is requested. Hence, this function is useful // when live var info is required for many (or all) instructions in a basic -// block. Also, the arguments to this method does not require specific +// block. Also, the arguments to this function does not require specific // iterators. //----------------------------------------------------------------------------- diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp index 0b680ab9e4..c22ede96b3 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp @@ -40,14 +40,14 @@ cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags, // RegisterAllocation pass front end... //---------------------------------------------------------------------------- namespace { - class RegisterAllocator : public MethodPass { + class RegisterAllocator : public FunctionPass { TargetMachine &Target; public: inline RegisterAllocator(TargetMachine &T) : Target(T) {} - bool runOnMethod(Function *F) { + bool runOnFunction(Function *F) { if (DEBUG_RA) - cerr << "\n******************** Method "<< F->getName() + cerr << "\n******************** Function "<< F->getName() << " ********************\n"; PhyRegAlloc PRA(F, Target, &getAnalysis<MethodLiveVarInfo>(), @@ -58,17 +58,14 @@ namespace { return false; } - virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires, - Pass::AnalysisSet &Destroyed, - Pass::AnalysisSet &Provided) { - Requires.push_back(cfg::LoopInfo::ID); - Requires.push_back(MethodLiveVarInfo::ID); - Destroyed.push_back(MethodLiveVarInfo::ID); + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(cfg::LoopInfo::ID); + AU.addRequired(MethodLiveVarInfo::ID); } }; } -MethodPass *getRegisterAllocator(TargetMachine &T) { +Pass *getRegisterAllocator(TargetMachine &T) { return new RegisterAllocator(T); } diff --git a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp index a46f2ef729..83e5487165 100644 --- a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp +++ b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp @@ -4,10 +4,10 @@ // LLVM. The code in this file assumes that the specified module has already // been compiled into the internal data structures of the Module. // -// This code largely consists of two LLVM Pass's: a MethodPass and a Pass. The -// MethodPass is pipelined together with all of the rest of the code generation -// stages, and the Pass runs at the end to emit code for global variables and -// such. +// This code largely consists of two LLVM Pass's: a FunctionPass and a Pass. +// The FunctionPass is pipelined together with all of the rest of the code +// generation stages, and the Pass runs at the end to emit code for global +// variables and such. // //===----------------------------------------------------------------------===// @@ -197,7 +197,7 @@ public: // SparcFunctionAsmPrinter Code //===----------------------------------------------------------------------===// -struct SparcFunctionAsmPrinter : public MethodPass, public AsmPrinter { +struct SparcFunctionAsmPrinter : public FunctionPass, public AsmPrinter { inline SparcFunctionAsmPrinter(std::ostream &os, const TargetMachine &t) : AsmPrinter(os, t) {} @@ -206,7 +206,7 @@ struct SparcFunctionAsmPrinter : public MethodPass, public AsmPrinter { return false; } - virtual bool runOnMethod(Function *F) { + virtual bool runOnFunction(Function *F) { startFunction(F); emitFunction(F); endFunction(F); @@ -410,7 +410,7 @@ SparcFunctionAsmPrinter::emitFunction(const Function *M) } // End anonymous namespace -Pass *UltraSparc::getMethodAsmPrinterPass(PassManager &PM, std::ostream &Out) { +Pass *UltraSparc::getFunctionAsmPrinterPass(PassManager &PM, std::ostream &Out){ return new SparcFunctionAsmPrinter(Out, *this); } diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h index 12c86b8b8d..0e80179f4e 100644 --- a/lib/Target/SparcV9/SparcV9Internals.h +++ b/lib/Target/SparcV9/SparcV9Internals.h @@ -128,7 +128,7 @@ public: // returned in `minstrVec'. Any temporary registers (TmpInstruction) // created are returned in `tempVec'. // - virtual void CreateCodeToLoadConst(Function* method, + virtual void CreateCodeToLoadConst(Function *F, Value* val, Instruction* dest, std::vector<MachineInstr*>& minstrVec, @@ -141,7 +141,7 @@ public: // The generated instructions are returned in `minstrVec'. // Any temp. registers (TmpInstruction) created are returned in `tempVec'. // - virtual void CreateCodeToCopyIntToFloat(Function* method, + virtual void CreateCodeToCopyIntToFloat(Function* F, Value* val, Instruction* dest, std::vector<MachineInstr*>& minstr, @@ -152,7 +152,7 @@ public: // `val' to an integer value `dest' by copying to memory and back. // See the previous function for information about return values. // - virtual void CreateCodeToCopyFloatToInt(Function* method, + virtual void CreateCodeToCopyFloatToInt(Function* F, Value* val, Instruction* dest, std::vector<MachineInstr*>& minstr, @@ -161,7 +161,7 @@ public: // create copy instruction(s) virtual void CreateCopyInstructionsByType(const TargetMachine& target, - Function* method, + Function* F, Value* src, Instruction* dest, std::vector<MachineInstr*>& minstr) const; @@ -224,7 +224,7 @@ class UltraSparcRegInfo : public MachineRegInfo { // ======================== Private Methods ============================= // The following methods are used to color special live ranges (e.g. - // method args and return values etc.) with specific hardware registers + // function args and return values etc.) with specific hardware registers // as required. See SparcRegInfo.cpp for the implementation. // void setCallOrRetArgCol(LiveRange *LR, unsigned RegNo, @@ -251,7 +251,7 @@ class UltraSparcRegInfo : public MachineRegInfo { unsigned getCallInstNumArgs(const MachineInstr *CallMI) const; - // The following 3 methods are used to find the RegType (see enum above) + // The following 3 methods are used to find the RegType (see enum above) // of a LiveRange, Value and using the unified RegClassID int getRegType(const LiveRange *LR) const; int getRegType(const Value *Val) const; @@ -272,7 +272,7 @@ class UltraSparcRegInfo : public MachineRegInfo { // The following 2 methods are used to order the instructions addeed by - // the register allocator in association with method calling. See + // the register allocator in association with function calling. See // SparcRegInfo.cpp for more details // void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec, @@ -344,7 +344,7 @@ public: virtual int getZeroRegNum() const; // getCallAddressReg - returns the reg used for pushing the address when a - // method is called. This can be used for other purposes between calls + // function is called. This can be used for other purposes between calls // unsigned getCallAddressReg() const; @@ -357,7 +357,7 @@ public: // The following methods are used to color special live ranges (e.g. - // method args and return values etc.) with specific hardware registers + // function args and return values etc.) with specific hardware registers // as required. See SparcRegInfo.cpp for the implementation for Sparc. // void suggestRegs4MethodArgs(const Function *Meth, @@ -499,16 +499,16 @@ public: UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {} public: - int getStackFrameSizeAlignment () const { return StackFrameSizeAlignment;} - int getMinStackFrameSize () const { return MinStackFrameSize; } - int getNumFixedOutgoingArgs () const { return NumFixedOutgoingArgs; } - int getSizeOfEachArgOnStack () const { return SizeOfEachArgOnStack; } - bool argsOnStackHaveFixedSize () const { return true; } + int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;} + int getMinStackFrameSize() const { return MinStackFrameSize; } + int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; } + int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; } + bool argsOnStackHaveFixedSize() const { return true; } // // These methods compute offsets using the frame contents for a - // particular method. The frame contents are obtained from the - // MachineCodeInfoForMethod object for the given method. + // particular function. The frame contents are obtained from the + // MachineCodeInfoForMethod object for the given function. // int getFirstIncomingArgOffset (MachineCodeForMethod& mcInfo, bool& growUp) const @@ -623,7 +623,7 @@ public: virtual void addPassesToEmitAssembly(PassManager &PM, std::ostream &Out); private: - Pass *getMethodAsmPrinterPass(PassManager &PM, std::ostream &Out); + Pass *getFunctionAsmPrinterPass(PassManager &PM, std::ostream &Out); Pass *getModuleAsmPrinterPass(PassManager &PM, std::ostream &Out); Pass *getEmitBytecodeToAsmPass(std::ostream &Out); }; diff --git a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp index 2dad572020..17cd73bfc3 100644 --- a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp +++ b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp @@ -21,11 +21,11 @@ namespace { -class InsertPrologEpilogCode : public MethodPass { +class InsertPrologEpilogCode : public FunctionPass { TargetMachine &Target; public: InsertPrologEpilogCode(TargetMachine &T) : Target(T) {} - bool runOnMethod(Function *F) { + bool runOnFunction(Function *F) { MachineCodeForMethod &mcodeInfo = MachineCodeForMethod::get(F); if (!mcodeInfo.isCompiledAsLeafMethod()) { InsertPrologCode(F); diff --git a/lib/Target/SparcV9/SparcV9TargetMachine.cpp b/lib/Target/SparcV9/SparcV9TargetMachine.cpp index de778e2562..306b85a227 100644 --- a/ |