aboutsummaryrefslogtreecommitdiff
path: root/lib
diff options
context:
space:
mode:
Diffstat (limited to 'lib')
-rw-r--r--lib/CodeGen/MachineInstr.cpp8
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAG.cpp10
-rw-r--r--lib/Target/Alpha/AlphaAsmPrinter.cpp8
-rw-r--r--lib/Target/Alpha/AlphaRegisterInfo.cpp3
-rw-r--r--lib/Target/IA64/IA64AsmPrinter.cpp8
-rw-r--r--lib/Target/PowerPC/PPCAsmPrinter.cpp9
-rw-r--r--lib/Target/Sparc/SparcAsmPrinter.cpp9
-rwxr-xr-xlib/Target/X86/X86ATTAsmPrinter.cpp1
-rw-r--r--lib/Target/X86/X86InstrBuilder.h2
-rwxr-xr-xlib/Target/X86/X86IntelAsmPrinter.cpp6
-rwxr-xr-xlib/Target/X86/X86IntelAsmPrinter.h4
-rw-r--r--lib/Target/X86/X86RegisterInfo.cpp2
12 files changed, 16 insertions, 54 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 3d65dfd31b..367631c60e 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -141,7 +141,7 @@ MachineInstr::SetMachineOperandConst(unsigned i,
void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
assert(i < getNumOperands()); // must be explicit op
- operands[i].opType = MachineOperand::MO_MachineRegister;
+ operands[i].opType = MachineOperand::MO_VirtualRegister;
operands[i].contents.value = NULL;
operands[i].extra.regNum = regNum;
}
@@ -187,9 +187,6 @@ static void print(const MachineOperand &MO, std::ostream &OS,
if (MO.hasAllocatedReg())
OutputReg(OS, MO.getReg(), MRI);
break;
- case MachineOperand::MO_MachineRegister:
- OutputReg(OS, MO.getMachineRegNum(), MRI);
- break;
case MachineOperand::MO_SignExtendedImmed:
OS << (long)MO.getImmedValue();
break;
@@ -297,9 +294,6 @@ std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) {
OutputValue(OS, MO.getVRegValue());
}
break;
- case MachineOperand::MO_MachineRegister:
- OutputReg(OS, MO.getMachineRegNum());
- break;
case MachineOperand::MO_SignExtendedImmed:
OS << (long)MO.getImmedValue();
break;
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 3509b16b6a..2b7b877cb1 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -110,7 +110,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
MI->addRegOperand(R->getReg(), MachineOperand::Use);
} else if (GlobalAddressSDNode *TGA =
dyn_cast<GlobalAddressSDNode>(Op)) {
- MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset());
+ MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
} else if (BasicBlockSDNode *BB =
dyn_cast<BasicBlockSDNode>(Op)) {
MI->addMachineBasicBlockOperand(BB->getBasicBlock());
@@ -143,7 +143,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
MI->addConstantPoolIndexOperand(Idx, Offset);
} else if (ExternalSymbolSDNode *ES =
dyn_cast<ExternalSymbolSDNode>(Op)) {
- MI->addExternalSymbolOperand(ES->getSymbol(), false);
+ MI->addExternalSymbolOperand(ES->getSymbol());
} else {
assert(Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Flag &&
@@ -296,7 +296,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
// Add the asm string as an external symbol operand.
const char *AsmStr =
cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
- MI->addExternalSymbolOperand(AsmStr, false);
+ MI->addExternalSymbolOperand(AsmStr);
// Add all of the operand registers to the instruction.
for (unsigned i = 2; i != NumOps;) {
@@ -311,13 +311,13 @@ void ScheduleDAG::EmitNode(SDNode *Node,
case 1: // Use of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addMachineRegOperand(Reg, MachineOperand::Use);
+ MI->addRegOperand(Reg, MachineOperand::Use);
}
break;
case 2: // Def of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addMachineRegOperand(Reg, MachineOperand::Def);
+ MI->addRegOperand(Reg, MachineOperand::Def);
}
break;
case 3: { // Immediate.
diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp
index 435e8e84d8..1e360676b6 100644
--- a/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -77,7 +77,7 @@ FunctionPass *llvm::createAlphaCodePrinterPass (std::ostream &o,
void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
{
const MachineOperand &MO = MI->getOperand(opNum);
- if (MO.getType() == MachineOperand::MO_MachineRegister) {
+ if (MO.getType() == MachineOperand::MO_VirtualRegister) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
@@ -94,12 +94,6 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
- if (Value *V = MO.getVRegValueOrNull()) {
- O << "<" << V->getName() << ">";
- return;
- }
- // FALLTHROUGH
- case MachineOperand::MO_MachineRegister:
O << RI.get(MO.getReg()).Name;
return;
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 8f6310e439..85c9da8e64 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -263,7 +263,8 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
.addReg(Alpha::R29).addImm(curgpdist);
//evil const_cast until MO stuff setup to handle const
- BuildMI(MBB, MBBI, Alpha::ALTENT, 1).addGlobalAddress(const_cast<Function*>(MF.getFunction()), true);
+ BuildMI(MBB, MBBI, Alpha::ALTENT, 1)
+ .addGlobalAddress(const_cast<Function*>(MF.getFunction()));
// Get the number of bytes to allocate from the FrameInfo
long NumBytes = MFI->getStackSize();
diff --git a/lib/Target/IA64/IA64AsmPrinter.cpp b/lib/Target/IA64/IA64AsmPrinter.cpp
index 6895d328da..087fcc32d8 100644
--- a/lib/Target/IA64/IA64AsmPrinter.cpp
+++ b/lib/Target/IA64/IA64AsmPrinter.cpp
@@ -66,7 +66,7 @@ namespace {
// This method is used by the tablegen'erated instruction printer.
void printOperand(const MachineInstr *MI, unsigned OpNo){
const MachineOperand &MO = MI->getOperand(OpNo);
- if (MO.getType() == MachineOperand::MO_MachineRegister) {
+ if (MO.getType() == MachineOperand::MO_VirtualRegister) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
//XXX Bug Workaround: See note in Printer::doInitialization about %.
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
@@ -174,12 +174,6 @@ void IA64AsmPrinter::printOp(const MachineOperand &MO,
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
- if (Value *V = MO.getVRegValueOrNull()) {
- O << "<" << V->getName() << ">";
- return;
- }
- // FALLTHROUGH
- case MachineOperand::MO_MachineRegister:
O << RI.get(MO.getReg()).Name;
return;
diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 2cf10a2f9d..e85ce9fd6f 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -86,7 +86,7 @@ namespace {
void printOperand(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
- if (MO.getType() == MachineOperand::MO_MachineRegister) {
+ if (MO.getType() == MachineOperand::MO_VirtualRegister) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
@@ -353,13 +353,6 @@ void PPCAsmPrinter::printOp(const MachineOperand &MO) {
int new_symbol;
switch (MO.getType()) {
- case MachineOperand::MO_VirtualRegister:
- if (Value *V = MO.getVRegValueOrNull()) {
- O << "<" << V->getName() << ">";
- return;
- }
- // FALLTHROUGH
- case MachineOperand::MO_MachineRegister:
O << RI.get(MO.getReg()).Name;
return;
diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp
index ced2b3dd0c..2d81bbd670 100644
--- a/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -147,12 +147,6 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
}
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
- if (Value *V = MO.getVRegValueOrNull()) {
- O << "<" << V->getName() << ">";
- break;
- }
- // FALLTHROUGH
- case MachineOperand::MO_MachineRegister:
if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
O << "%" << LowercaseString (RI.get(MO.getReg()).Name);
else
@@ -195,8 +189,7 @@ void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
- if ((OpTy == MachineOperand::MO_VirtualRegister ||
- OpTy == MachineOperand::MO_MachineRegister) &&
+ if (OpTy == MachineOperand::MO_VirtualRegister &&
MI->getOperand(opNum+1).getReg() == SP::G0)
return; // don't print "+%g0"
if ((OpTy == MachineOperand::MO_SignExtendedImmed ||
diff --git a/lib/Target/X86/X86ATTAsmPrinter.cpp b/lib/Target/X86/X86ATTAsmPrinter.cpp
index b7f5b6c8a6..5283ddd79e 100755
--- a/lib/Target/X86/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/X86ATTAsmPrinter.cpp
@@ -109,7 +109,6 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
- case MachineOperand::MO_MachineRegister:
assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Virtual registers should not make it this far!");
O << '%';
diff --git a/lib/Target/X86/X86InstrBuilder.h b/lib/Target/X86/X86InstrBuilder.h
index 95d7f927d8..6a3c116f6d 100644
--- a/lib/Target/X86/X86InstrBuilder.h
+++ b/lib/Target/X86/X86InstrBuilder.h
@@ -93,7 +93,7 @@ inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
assert (0);
MIB.addZImm(AM.Scale).addReg(AM.IndexReg);
if (AM.GV)
- return MIB.addGlobalAddress(AM.GV, false, AM.Disp);
+ return MIB.addGlobalAddress(AM.GV, AM.Disp);
else
return MIB.addSImm(AM.Disp);
}
diff --git a/lib/Target/X86/X86IntelAsmPrinter.cpp b/lib/Target/X86/X86IntelAsmPrinter.cpp
index f3213b64f4..f9093da36d 100755
--- a/lib/Target/X86/X86IntelAsmPrinter.cpp
+++ b/lib/Target/X86/X86IntelAsmPrinter.cpp
@@ -115,12 +115,6 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
- if (Value *V = MO.getVRegValueOrNull()) {
- O << "<" << V->getName() << ">";
- return;
- }
- // FALLTHROUGH
- case MachineOperand::MO_MachineRegister:
if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
O << RI.get(MO.getReg()).Name;
else
diff --git a/lib/Target/X86/X86IntelAsmPrinter.h b/lib/Target/X86/X86IntelAsmPrinter.h
index b408ea3903..28ccfc9ed0 100755
--- a/lib/Target/X86/X86IntelAsmPrinter.h
+++ b/lib/Target/X86/X86IntelAsmPrinter.h
@@ -37,8 +37,8 @@ struct X86IntelAsmPrinter : public X86SharedAsmPrinter {
void printOperand(const MachineInstr *MI, unsigned OpNo,
const char *Modifier = 0) {
const MachineOperand &MO = MI->getOperand(OpNo);
- if (MO.getType() == MachineOperand::MO_MachineRegister) {
- assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
+ if (MO.getType() == MachineOperand::MO_VirtualRegister) {
+ assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else {
printOp(MO, Modifier);
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 383529a0eb..a9e345fc68 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -150,7 +150,7 @@ static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
else if (MI->getOperand(1).isGlobalAddress())
return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
.addGlobalAddress(MI->getOperand(1).getGlobal(),
- false, MI->getOperand(1).getOffset());
+ MI->getOperand(1).getOffset());
else if (MI->getOperand(1).isJumpTableIndex())
return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
.addJumpTableIndex(MI->getOperand(1).getJumpTableIndex());
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-04 00:10:49 +0000