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-rw-r--r--lib/CodeGen/SelectionDAG/FastISel.cpp26
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp6
-rw-r--r--lib/Target/X86/X86FastISel.h5
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp6
-rw-r--r--lib/Target/X86/X86ISelLowering.h4
5 files changed, 22 insertions, 25 deletions
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 3ff8148e99..70e0248c23 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -16,6 +16,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetMachine.h"
using namespace llvm;
/// SelectBinaryOp - Select and emit code for a binary operator instruction,
@@ -54,7 +55,9 @@ bool FastISel::SelectGetElementPtr(Instruction *I,
BasicBlock::iterator
FastISel::SelectInstructions(BasicBlock::iterator Begin,
BasicBlock::iterator End,
- DenseMap<const Value*, unsigned> &ValueMap) {
+ DenseMap<const Value*, unsigned> &ValueMap,
+ MachineBasicBlock *mbb) {
+ MBB = mbb;
BasicBlock::iterator I = Begin;
for (; I != End; ++I) {
@@ -108,7 +111,7 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
if (BI->isUnconditional()) {
MachineFunction::iterator NextMBB =
next(MachineFunction::iterator(MBB));
- if (NextMBB != MF->end() &&
+ if (NextMBB != MF.end() &&
NextMBB->getBasicBlock() == BI->getSuccessor(0)) {
MBB->addSuccessor(NextMBB);
break;
@@ -127,6 +130,10 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
return I;
}
+FastISel::FastISel(MachineFunction &mf)
+ : MF(mf), MRI(mf.getRegInfo()), TII(*mf.getTarget().getInstrInfo()) {
+}
+
FastISel::~FastISel() {}
unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
@@ -145,11 +152,10 @@ unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
const TargetRegisterClass* RC) {
- MachineRegisterInfo &MRI = MF->getRegInfo();
unsigned ResultReg = MRI.createVirtualRegister(RC);
- const TargetInstrDesc &II = TII->get(MachineInstOpcode);
+ const TargetInstrDesc &II = TII.get(MachineInstOpcode);
- MachineInstr *MI = BuildMI(*MF, II, ResultReg);
+ MachineInstr *MI = BuildMI(MF, II, ResultReg);
MBB->push_back(MI);
return ResultReg;
}
@@ -157,11 +163,10 @@ unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0) {
- MachineRegisterInfo &MRI = MF->getRegInfo();
unsigned ResultReg = MRI.createVirtualRegister(RC);
- const TargetInstrDesc &II = TII->get(MachineInstOpcode);
+ const TargetInstrDesc &II = TII.get(MachineInstOpcode);
- MachineInstr *MI = BuildMI(*MF, II, ResultReg).addReg(Op0);
+ MachineInstr *MI = BuildMI(MF, II, ResultReg).addReg(Op0);
MBB->push_back(MI);
return ResultReg;
}
@@ -169,11 +174,10 @@ unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
const TargetRegisterClass *RC,
unsigned Op0, unsigned Op1) {
- MachineRegisterInfo &MRI = MF->getRegInfo();
unsigned ResultReg = MRI.createVirtualRegister(RC);
- const TargetInstrDesc &II = TII->get(MachineInstOpcode);
+ const TargetInstrDesc &II = TII.get(MachineInstOpcode);
- MachineInstr *MI = BuildMI(*MF, II, ResultReg).addReg(Op0).addReg(Op1);
+ MachineInstr *MI = BuildMI(MF, II, ResultReg).addReg(Op0).addReg(Op1);
MBB->push_back(MI);
return ResultReg;
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 997bd11604..9ffb6ccc4a 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -5111,9 +5111,9 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
!BB->isLandingPad() &&
isa<BranchInst>(LLVMBB->getTerminator()) &&
cast<BranchInst>(LLVMBB->getTerminator())->isUnconditional()) {
- if (FastISel *F = TLI.createFastISel(BB, &FuncInfo.MF,
- TLI.getTargetMachine().getInstrInfo())) {
- Begin = F->SelectInstructions(Begin, LLVMBB->end(), FuncInfo.ValueMap);
+ if (FastISel *F = TLI.createFastISel(FuncInfo.MF)) {
+ Begin = F->SelectInstructions(Begin, LLVMBB->end(),
+ FuncInfo.ValueMap, BB);
// Clean up the FastISel object. TODO: Reorganize what data is
// stored in the FastISel class itself and what is merely passed
diff --git a/lib/Target/X86/X86FastISel.h b/lib/Target/X86/X86FastISel.h
index 0f2b26a4d2..56dfc4f4b9 100644
--- a/lib/Target/X86/X86FastISel.h
+++ b/lib/Target/X86/X86FastISel.h
@@ -18,14 +18,11 @@
namespace llvm {
class FastISel;
-class MachineBasicBlock;
class MachineFunction;
-class TargetInstrInfo;
namespace X86 {
-FastISel *createFastISel(MachineBasicBlock *mbb, MachineFunction *mf,
- const TargetInstrInfo *tii);
+FastISel *createFastISel(MachineFunction &mf);
} // namespace X86
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index c43ce33c8c..9a77c8e61c 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1872,10 +1872,8 @@ bool X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Call,
return false;
}
-FastISel *X86TargetLowering::createFastISel(MachineBasicBlock *mbb,
- MachineFunction *mf,
- const TargetInstrInfo *tii) {
- return X86::createFastISel(mbb, mf, tii);
+FastISel *X86TargetLowering::createFastISel(MachineFunction &mf) {
+ return X86::createFastISel(mf);
}
diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index 1415be7b63..c35cce2c81 100644
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -469,9 +469,7 @@ namespace llvm {
/// createFastISel - This method returns a target specific FastISel object,
/// or null if the target does not support "fast" ISel.
- virtual FastISel *createFastISel(MachineBasicBlock *mbb,
- MachineFunction *mf,
- const TargetInstrInfo *tii);
+ virtual FastISel *createFastISel(MachineFunction &mf);
private:
/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-04 20:34:46 +0000