diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrFragmentsSIMD.td | 4 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 31 |
3 files changed, 22 insertions, 15 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index d74a87281c..cf90490703 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -8697,7 +8697,7 @@ SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const { SDValue Op2 = Op.getOperand(2); DebugLoc DL = Op.getDebugLoc(); - SDValue Ops[] = {Cond, Op1, Op2}; + SDValue Ops[] = {Op1, Op2, Cond}; assert(Op1.getValueType().isVector() && "Op1 must be a vector"); assert(Op2.getValueType().isVector() && "Op2 must be a vector"); diff --git a/lib/Target/X86/X86InstrFragmentsSIMD.td b/lib/Target/X86/X86InstrFragmentsSIMD.td index 7ad9c87d28..c2db9177cd 100644 --- a/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -61,10 +61,10 @@ def X86psignd : SDNode<"X86ISD::PSIGND", def X86pblendvb : SDNode<"X86ISD::PBLENDVB", SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>; -def X86blendvpd : SDNode<"X86ISD::BLENDVPD", +def X86blendvpd : SDNode<"X86ISD::BLENDVPD", SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>; -def X86blendvps : SDNode<"X86ISD::BLENDVPS", +def X86blendvps : SDNode<"X86ISD::BLENDVPS", SDTypeProfile<1, 3, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>; def X86pextrb : SDNode<"X86ISD::PEXTRB", diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 9148c76ce0..6bcba728ae 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -5853,9 +5853,14 @@ defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem, defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem, memopv32i8, int_x86_avx_blendv_ps_256>; -def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, VR128:$src3), - (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$src3)>, - Requires<[HasAVX]>; +let Predicates = [HasAVX] in { + def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, VR128:$mask), + (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>; + def : Pat<(X86blendvpd VR128:$src1, VR128:$src2, VR128:$mask), + (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>; + def : Pat<(X86blendvps VR128:$src1, VR128:$src2, VR128:$mask), + (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>; +} /// SS41I_ternary_int - SSE 4.1 ternary operator let Uses = [XMM0], Constraints = "$src1 = $dst" in { @@ -5877,16 +5882,18 @@ let Uses = [XMM0], Constraints = "$src1 = $dst" in { } } -defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>; -defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>; -defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>; +defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>; +defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>; +defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>; -def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, XMM0), - (PBLENDVBrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>; -def : Pat<(X86blendvpd XMM0, VR128:$src1, VR128:$src2), - (BLENDVPDrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>; -def : Pat<(X86blendvps XMM0, VR128:$src1, VR128:$src2), - (BLENDVPSrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>; +let Predicates = [HasSSE41] in { + def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, XMM0), + (PBLENDVBrr0 VR128:$src1, VR128:$src2)>; + def : Pat<(X86blendvpd VR128:$src1, VR128:$src2, XMM0), + (BLENDVPDrr0 VR128:$src1, VR128:$src2)>; + def : Pat<(X86blendvps VR128:$src1, VR128:$src2, XMM0), + (BLENDVPSrr0 VR128:$src1, VR128:$src2)>; +} let Predicates = [HasAVX] in def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), |