diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 29 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 10 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 8 |
3 files changed, 28 insertions, 19 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index afaea04b9d..bd7fa5cf6c 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -544,6 +544,24 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); } + // FIXME: handle tail calls differently. + unsigned CallOpc; + if (Subtarget->isThumb()) { + if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc)) + CallOpc = ARMISD::CALL_NOLINK; + else + CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; + } else { + CallOpc = (isDirect || Subtarget->hasV5TOps()) + ? ARMISD::CALL : ARMISD::CALL_NOLINK; + } + if (CallOpc == ARMISD::CALL_NOLINK) { + // On CALL_NOLINK we must move PC to LR + Chain = DAG.getCopyToReg(Chain, ARM::LR, + DAG.getRegister(ARM::PC, MVT::i32), InFlag); + InFlag = Chain.getValue(1); + } + std::vector<MVT::ValueType> NodeTys; NodeTys.push_back(MVT::Other); // Returns a chain NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. @@ -558,17 +576,6 @@ SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { Ops.push_back(DAG.getRegister(RegsToPass[i].first, RegsToPass[i].second.getValueType())); - // FIXME: handle tail calls differently. - unsigned CallOpc; - if (Subtarget->isThumb()) { - if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc)) - CallOpc = ARMISD::CALL_NOLINK; - else - CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; - } else { - CallOpc = (isDirect || Subtarget->hasV5TOps()) - ? ARMISD::CALL : ARMISD::CALL_NOLINK; - } if (InFlag.Val) Ops.push_back(InFlag); Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index bb8b61f0b3..201f65c7f5 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -370,8 +370,6 @@ class AI3<dag ops, string asm, list<dag> pattern> : I<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>; class AI4<dag ops, string asm, list<dag> pattern> : I<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>; -class AIx2<dag ops, string asm, list<dag> pattern> - : I<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>; class AI1x2<dag ops, string asm, list<dag> pattern> : I<ops, AddrMode1, Size8Bytes, IndexModeNone, asm, "", pattern>; @@ -546,10 +544,12 @@ let isCall = 1, noResults = 1, def BLX : AI<(ops GPR:$dst, variable_ops), "blx $dst", [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>; - // ARMv4T - def BX : AIx2<(ops GPR:$dst, variable_ops), - "mov lr, pc\n\tbx $dst", + let Uses = [LR] in { + // ARMv4T + def BX : AI<(ops GPR:$dst, variable_ops), + "bx $dst", [(ARMcall_nolink GPR:$dst)]>; + } } let isBranch = 1, isTerminator = 1, isBarrier = 1 in { diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 3c7cd03ee7..a1f03bd172 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -189,10 +189,12 @@ let isCall = 1, noResults = 1, def tBLXr : TI<(ops GPR:$dst, variable_ops), "blx $dst", [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>; - // ARMv4T - def tBX : TIx2<(ops GPR:$dst, variable_ops), - "cpy lr, pc\n\tbx $dst", + let Uses = [LR] in { + // ARMv4T + def tBX : TI<(ops GPR:$dst, variable_ops), + "bx $dst", [(ARMcall_nolink GPR:$dst)]>; + } } let isBranch = 1, isTerminator = 1, isBarrier = 1 in { |