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-rw-r--r--lib/Target/SparcV9/SparcV9InstrInfo.cpp2
-rw-r--r--lib/Target/SparcV9/SparcV9InstrSelection.cpp4
2 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/SparcV9/SparcV9InstrInfo.cpp b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
index 6df7617c93..8bdb0f2966 100644
--- a/lib/Target/SparcV9/SparcV9InstrInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
@@ -443,7 +443,7 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
if (opSize > destSize ||
(val->getType()->isSigned()
- && destSize < target.getTargetData().getIntegerRegize()))
+ && destSize < target.getTargetData().getIntegerRegSize()))
{ // operand is larger than dest,
// OR both are equal but smaller than the full register size
// AND operand is signed, so it may have extra sign bits:
diff --git a/lib/Target/SparcV9/SparcV9InstrSelection.cpp b/lib/Target/SparcV9/SparcV9InstrSelection.cpp
index 73e3b1ce6f..50e2fe23d4 100644
--- a/lib/Target/SparcV9/SparcV9InstrSelection.cpp
+++ b/lib/Target/SparcV9/SparcV9InstrSelection.cpp
@@ -759,7 +759,7 @@ CreateShiftInstructions(const TargetMachine& target,
Value* shiftDest = destVal;
unsigned opSize = target.getTargetData().getTypeSize(argVal1->getType());
if ((shiftOpCode == SLL || shiftOpCode == SLLX)
- && opSize < target.getTargetData().getIntegerRegize())
+ && opSize < target.getTargetData().getIntegerRegSize())
{ // put SLL result into a temporary
shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp");
mcfi.addTemp(shiftDest);
@@ -2305,7 +2305,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
.addReg(dest, MOTy::Def);
mvec.push_back(M);
}
- else if (destSize < target.getTargetData().getIntegerRegize())
+ else if (destSize < target.getTargetData().getIntegerRegSize())
assert(0 && "Unsupported type size: 32 < size < 64 bits");
}
}