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-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp1402
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeDAG.cpp866
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp246
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp482
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeTypes.cpp118
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeTypes.h424
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp86
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp194
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAG.cpp40
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp8
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp744
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp494
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp2
-rw-r--r--lib/CodeGen/SelectionDAG/TargetLowering.cpp108
-rw-r--r--lib/Target/ARM/ARMAddressingModes.h2
-rw-r--r--lib/Target/ARM/ARMISelDAGToDAG.cpp242
-rw-r--r--lib/Target/ARM/ARMISelLowering.cpp320
-rw-r--r--lib/Target/ARM/ARMISelLowering.h40
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td2
-rw-r--r--lib/Target/Alpha/AlphaISelDAGToDAG.cpp100
-rw-r--r--lib/Target/Alpha/AlphaISelLowering.cpp128
-rw-r--r--lib/Target/Alpha/AlphaISelLowering.h12
-rw-r--r--lib/Target/Alpha/AlphaInstrInfo.td2
-rw-r--r--lib/Target/CellSPU/SPUISelDAGToDAG.cpp90
-rw-r--r--lib/Target/CellSPU/SPUISelLowering.cpp576
-rw-r--r--lib/Target/CellSPU/SPUISelLowering.h26
-rw-r--r--lib/Target/CellSPU/SPUOperands.td4
-rw-r--r--lib/Target/IA64/IA64ISelDAGToDAG.cpp198
-rw-r--r--lib/Target/IA64/IA64ISelLowering.cpp64
-rw-r--r--lib/Target/IA64/IA64ISelLowering.h12
-rw-r--r--lib/Target/Mips/MipsISelDAGToDAG.cpp76
-rw-r--r--lib/Target/Mips/MipsISelLowering.cpp152
-rw-r--r--lib/Target/Mips/MipsISelLowering.h26
-rw-r--r--lib/Target/PIC16/PIC16ISelDAGToDAG.cpp28
-rw-r--r--lib/Target/PIC16/PIC16ISelLowering.cpp134
-rw-r--r--lib/Target/PIC16/PIC16ISelLowering.h22
-rw-r--r--lib/Target/PowerPC/PPCHazardRecognizers.cpp2
-rw-r--r--lib/Target/PowerPC/PPCHazardRecognizers.h4
-rw-r--r--lib/Target/PowerPC/PPCISelDAGToDAG.cpp216
-rw-r--r--lib/Target/PowerPC/PPCISelLowering.cpp746
-rw-r--r--lib/Target/PowerPC/PPCISelLowering.h104
-rw-r--r--lib/Target/Sparc/SparcISelDAGToDAG.cpp34
-rw-r--r--lib/Target/Sparc/SparcISelLowering.cpp168
-rw-r--r--lib/Target/Sparc/SparcISelLowering.h6
-rw-r--r--lib/Target/X86/X86ISelDAGToDAG.cpp258
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp1130
-rw-r--r--lib/Target/X86/X86ISelLowering.h146
-rw-r--r--lib/Target/X86/X86InstrInfo.cpp14
-rw-r--r--lib/Transforms/Scalar/CodeGenPrepare.cpp2
49 files changed, 5147 insertions, 5153 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index e6c3314b24..747a0b1e54 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -70,7 +70,7 @@ namespace {
/// visit - call the node-specific routine that knows how to fold each
/// particular type of node.
- SDOperand visit(SDNode *N);
+ SDValue visit(SDNode *N);
public:
/// AddToWorkList - Add to the work list making sure it's instance is at the
@@ -87,16 +87,16 @@ namespace {
WorkList.end());
}
- SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
+ SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
bool AddTo = true);
- SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
+ SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
return CombineTo(N, &Res, 1, AddTo);
}
- SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
+ SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
bool AddTo = true) {
- SDOperand To[] = { Res0, Res1 };
+ SDValue To[] = { Res0, Res1 };
return CombineTo(N, To, 2, AddTo);
}
@@ -105,12 +105,12 @@ namespace {
/// SimplifyDemandedBits - Check the specified integer node value to see if
/// it can be simplified or if things it uses can be simplified by bit
/// propagation. If so, return true.
- bool SimplifyDemandedBits(SDOperand Op) {
+ bool SimplifyDemandedBits(SDValue Op) {
APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits());
return SimplifyDemandedBits(Op, Demanded);
}
- bool SimplifyDemandedBits(SDOperand Op, const APInt &Demanded);
+ bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
bool CombineToPreIndexedLoadStore(SDNode *N);
bool CombineToPostIndexedLoadStore(SDNode *N);
@@ -119,122 +119,122 @@ namespace {
/// combine - call the node-specific routine that knows how to fold each
/// particular type of node. If that doesn't do anything, try the
/// target-specific DAG combines.
- SDOperand combine(SDNode *N);
+ SDValue combine(SDNode *N);
// Visitation implementation - Implement dag node combining for different
// node types. The semantics are as follows:
// Return Value:
- // SDOperand.Val == 0 - No change was made
- // SDOperand.Val == N - N was replaced, is dead, and is already handled.
+ // SDValue.Val == 0 - No change was made
+ // SDValue.Val == N - N was replaced, is dead, and is already handled.
// otherwise - N should be replaced by the returned Operand.
//
- SDOperand visitTokenFactor(SDNode *N);
- SDOperand visitMERGE_VALUES(SDNode *N);
- SDOperand visitADD(SDNode *N);
- SDOperand visitSUB(SDNode *N);
- SDOperand visitADDC(SDNode *N);
- SDOperand visitADDE(SDNode *N);
- SDOperand visitMUL(SDNode *N);
- SDOperand visitSDIV(SDNode *N);
- SDOperand visitUDIV(SDNode *N);
- SDOperand visitSREM(SDNode *N);
- SDOperand visitUREM(SDNode *N);
- SDOperand visitMULHU(SDNode *N);
- SDOperand visitMULHS(SDNode *N);
- SDOperand visitSMUL_LOHI(SDNode *N);
- SDOperand visitUMUL_LOHI(SDNode *N);
- SDOperand visitSDIVREM(SDNode *N);
- SDOperand visitUDIVREM(SDNode *N);
- SDOperand visitAND(SDNode *N);
- SDOperand visitOR(SDNode *N);
- SDOperand visitXOR(SDNode *N);
- SDOperand SimplifyVBinOp(SDNode *N);
- SDOperand visitSHL(SDNode *N);
- SDOperand visitSRA(SDNode *N);
- SDOperand visitSRL(SDNode *N);
- SDOperand visitCTLZ(SDNode *N);
- SDOperand visitCTTZ(SDNode *N);
- SDOperand visitCTPOP(SDNode *N);
- SDOperand visitSELECT(SDNode *N);
- SDOperand visitSELECT_CC(SDNode *N);
- SDOperand visitSETCC(SDNode *N);
- SDOperand visitSIGN_EXTEND(SDNode *N);
- SDOperand visitZERO_EXTEND(SDNode *N);
- SDOperand visitANY_EXTEND(SDNode *N);
- SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
- SDOperand visitTRUNCATE(SDNode *N);
- SDOperand visitBIT_CONVERT(SDNode *N);
- SDOperand visitBUILD_PAIR(SDNode *N);
- SDOperand visitFADD(SDNode *N);
- SDOperand visitFSUB(SDNode *N);
- SDOperand visitFMUL(SDNode *N);
- SDOperand visitFDIV(SDNode *N);
- SDOperand visitFREM(SDNode *N);
- SDOperand visitFCOPYSIGN(SDNode *N);
- SDOperand visitSINT_TO_FP(SDNode *N);
- SDOperand visitUINT_TO_FP(SDNode *N);
- SDOperand visitFP_TO_SINT(SDNode *N);
- SDOperand visitFP_TO_UINT(SDNode *N);
- SDOperand visitFP_ROUND(SDNode *N);
- SDOperand visitFP_ROUND_INREG(SDNode *N);
- SDOperand visitFP_EXTEND(SDNode *N);
- SDOperand visitFNEG(SDNode *N);
- SDOperand visitFABS(SDNode *N);
- SDOperand visitBRCOND(SDNode *N);
- SDOperand visitBR_CC(SDNode *N);
- SDOperand visitLOAD(SDNode *N);
- SDOperand visitSTORE(SDNode *N);
- SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
- SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N);
- SDOperand visitBUILD_VECTOR(SDNode *N);
- SDOperand visitCONCAT_VECTORS(SDNode *N);
- SDOperand visitVECTOR_SHUFFLE(SDNode *N);
-
- SDOperand XformToShuffleWithZero(SDNode *N);
- SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
+ SDValue visitTokenFactor(SDNode *N);
+ SDValue visitMERGE_VALUES(SDNode *N);
+ SDValue visitADD(SDNode *N);
+ SDValue visitSUB(SDNode *N);
+ SDValue visitADDC(SDNode *N);
+ SDValue visitADDE(SDNode *N);
+ SDValue visitMUL(SDNode *N);
+ SDValue visitSDIV(SDNode *N);
+ SDValue visitUDIV(SDNode *N);
+ SDValue visitSREM(SDNode *N);
+ SDValue visitUREM(SDNode *N);
+ SDValue visitMULHU(SDNode *N);
+ SDValue visitMULHS(SDNode *N);
+ SDValue visitSMUL_LOHI(SDNode *N);
+ SDValue visitUMUL_LOHI(SDNode *N);
+ SDValue visitSDIVREM(SDNode *N);
+ SDValue visitUDIVREM(SDNode *N);
+ SDValue visitAND(SDNode *N);
+ SDValue visitOR(SDNode *N);
+ SDValue visitXOR(SDNode *N);
+ SDValue SimplifyVBinOp(SDNode *N);
+ SDValue visitSHL(SDNode *N);
+ SDValue visitSRA(SDNode *N);
+ SDValue visitSRL(SDNode *N);
+ SDValue visitCTLZ(SDNode *N);
+ SDValue visitCTTZ(SDNode *N);
+ SDValue visitCTPOP(SDNode *N);
+ SDValue visitSELECT(SDNode *N);
+ SDValue visitSELECT_CC(SDNode *N);
+ SDValue visitSETCC(SDNode *N);
+ SDValue visitSIGN_EXTEND(SDNode *N);
+ SDValue visitZERO_EXTEND(SDNode *N);
+ SDValue visitANY_EXTEND(SDNode *N);
+ SDValue visitSIGN_EXTEND_INREG(SDNode *N);
+ SDValue visitTRUNCATE(SDNode *N);
+ SDValue visitBIT_CONVERT(SDNode *N);
+ SDValue visitBUILD_PAIR(SDNode *N);
+ SDValue visitFADD(SDNode *N);
+ SDValue visitFSUB(SDNode *N);
+ SDValue visitFMUL(SDNode *N);
+ SDValue visitFDIV(SDNode *N);
+ SDValue visitFREM(SDNode *N);
+ SDValue visitFCOPYSIGN(SDNode *N);
+ SDValue visitSINT_TO_FP(SDNode *N);
+ SDValue visitUINT_TO_FP(SDNode *N);
+ SDValue visitFP_TO_SINT(SDNode *N);
+ SDValue visitFP_TO_UINT(SDNode *N);
+ SDValue visitFP_ROUND(SDNode *N);
+ SDValue visitFP_ROUND_INREG(SDNode *N);
+ SDValue visitFP_EXTEND(SDNode *N);
+ SDValue visitFNEG(SDNode *N);
+ SDValue visitFABS(SDNode *N);
+ SDValue visitBRCOND(SDNode *N);
+ SDValue visitBR_CC(SDNode *N);
+ SDValue visitLOAD(SDNode *N);
+ SDValue visitSTORE(SDNode *N);
+ SDValue visitINSERT_VECTOR_ELT(SDNode *N);
+ SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
+ SDValue visitBUILD_VECTOR(SDNode *N);
+ SDValue visitCONCAT_VECTORS(SDNode *N);
+ SDValue visitVECTOR_SHUFFLE(SDNode *N);
+
+ SDValue XformToShuffleWithZero(SDNode *N);
+ SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS);
- SDOperand visitShiftByConstant(SDNode *N, unsigned Amt);
+ SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
- bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
- SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
- SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
- SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
- SDOperand N3, ISD::CondCode CC,
+ bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
+ SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
+ SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2);
+ SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2,
+ SDValue N3, ISD::CondCode CC,
bool NotExtCompare = false);
- SDOperand SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
+ SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
ISD::CondCode Cond, bool foldBooleans = true);
- SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
+ SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
unsigned HiOp);
- SDOperand CombineConsecutiveLoads(SDNode *N, MVT VT);
- SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
- SDOperand BuildSDIV(SDNode *N);
- SDOperand BuildUDIV(SDNode *N);
- SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
- SDOperand ReduceLoadWidth(SDNode *N);
+ SDValue CombineConsecutiveLoads(SDNode *N, MVT VT);
+ SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
+ SDValue BuildSDIV(SDNode *N);
+ SDValue BuildUDIV(SDNode *N);
+ SDNode *MatchRotate(SDValue LHS, SDValue RHS);
+ SDValue ReduceLoadWidth(SDNode *N);
- SDOperand GetDemandedBits(SDOperand V, const APInt &Mask);
+ SDValue GetDemandedBits(SDValue V, const APInt &Mask);
/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
/// looking for aliasing nodes and adding them to the Aliases vector.
- void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
- SmallVector<SDOperand, 8> &Aliases);
+ void GatherAllAliases(SDNode *N, SDValue OriginalChain,
+ SmallVector<SDValue, 8> &Aliases);
/// isAlias - Return true if there is any possibility that the two addresses
/// overlap.
- bool isAlias(SDOperand Ptr1, int64_t Size1,
+ bool isAlias(SDValue Ptr1, int64_t Size1,
const Value *SrcValue1, int SrcValueOffset1,
- SDOperand Ptr2, int64_t Size2,
+ SDValue Ptr2, int64_t Size2,
const Value *SrcValue2, int SrcValueOffset2);
/// FindAliasInfo - Extracts the relevant alias information from the memory
/// node. Returns true if the operand was a load.
bool FindAliasInfo(SDNode *N,
- SDOperand &Ptr, int64_t &Size,
+ SDValue &Ptr, int64_t &Size,
const Value *&SrcValue, int &SrcValueOffset);
/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
/// looking for a better chain (aliasing node.)
- SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
+ SDValue FindBetterChain(SDNode *N, SDValue Chain);
public:
DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
@@ -276,19 +276,19 @@ void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
((DAGCombiner*)DC)->AddToWorkList(N);
}
-SDOperand TargetLowering::DAGCombinerInfo::
-CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
+SDValue TargetLowering::DAGCombinerInfo::
+CombineTo(SDNode *N, const std::vector<SDValue> &To) {
return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
}
-SDOperand TargetLowering::DAGCombinerInfo::
-CombineTo(SDNode *N, SDOperand Res) {
+SDValue TargetLowering::DAGCombinerInfo::
+CombineTo(SDNode *N, SDValue Res) {
return ((DAGCombiner*)DC)->CombineTo(N, Res);
}
-SDOperand TargetLowering::DAGCombinerInfo::
-CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
+SDValue TargetLowering::DAGCombinerInfo::
+CombineTo(SDNode *N, SDValue Res0, SDValue Res1) {
return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
}
@@ -300,7 +300,7 @@ CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
/// isNegatibleForFree - Return 1 if we can compute the negated form of the
/// specified expression for the same cost as the expression itself, or 2 if we
/// can compute the negated form more cheaply than the expression itself.
-static char isNegatibleForFree(SDOperand Op, bool AfterLegalize,
+static char isNegatibleForFree(SDValue Op, bool AfterLegalize,
unsigned Depth = 0) {
// No compile time optimizations on this type.
if (Op.getValueType() == MVT::ppcf128)
@@ -356,7 +356,7 @@ static char isNegatibleForFree(SDOperand Op, bool AfterLegalize,
/// GetNegatedExpression - If isNegatibleForFree returns true, this function
/// returns the newly negated expression.
-static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
+static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
bool AfterLegalize, unsigned Depth = 0) {
// fneg is removable even if it has multiple uses.
if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
@@ -436,8 +436,8 @@ static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
// Also, set the incoming LHS, RHS, and CC references to the appropriate
// nodes based on the type of node we are checking. This simplifies life a
// bit for the callers.
-static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
- SDOperand &CC) {
+static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
+ SDValue &CC) {
if (N.getOpcode() == ISD::SETCC) {
LHS = N.getOperand(0);
RHS = N.getOperand(1);
@@ -460,24 +460,24 @@ static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
// one use. If this is true, it allows the users to invert the operation for
// free when it is profitable to do so.
-static bool isOneUseSetCC(SDOperand N) {
- SDOperand N0, N1, N2;
+static bool isOneUseSetCC(SDValue N) {
+ SDValue N0, N1, N2;
if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
return true;
return false;
}
-SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
+SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDValue N0, SDValue N1){
MVT VT = N0.getValueType();
// reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
// reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
if (isa<ConstantSDNode>(N1)) {
- SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
+ SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
AddToWorkList(OpNode.Val);
return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
} else if (N0.hasOneUse()) {
- SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
+ SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
AddToWorkList(OpNode.Val);
return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
}
@@ -486,20 +486,20 @@ SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
// reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
if (isa<ConstantSDNode>(N0)) {
- SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
+ SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
AddToWorkList(OpNode.Val);
return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
} else if (N1.hasOneUse()) {
- SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
+ SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
AddToWorkList(OpNode.Val);
return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
}
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
- bool AddTo) {
+SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
+ bool AddTo) {
assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
++NodesCombined;
DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
@@ -522,13 +522,13 @@ SDOperand DAGCombiner::CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
// Finally, since the node is now dead, remove it from the graph.
DAG.DeleteNode(N);
- return SDOperand(N, 0);
+ return SDValue(N, 0);
}
/// SimplifyDemandedBits - Check the specified integer node value to see if
/// it can be simplified or if things it uses can be simplified by bit
/// propagation. If so, return true.
-bool DAGCombiner::SimplifyDemandedBits(SDOperand Op, const APInt &Demanded) {
+bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize);
APInt KnownZero, KnownOne;
if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
@@ -590,7 +590,7 @@ void DAGCombiner::Run(bool RunningAfterLegalize) {
// The root of the dag may dangle to deleted nodes until the dag combiner is
// done. Set it to null to avoid confusion.
- DAG.setRoot(SDOperand());
+ DAG.setRoot(SDValue());
// while the worklist isn't empty, inspect the node on the end of it and
// try and combine it.
@@ -609,7 +609,7 @@ void DAGCombiner::Run(bool RunningAfterLegalize) {
continue;
}
- SDOperand RV = combine(N);
+ SDValue RV = combine(N);
if (RV.Val == 0)
continue;
@@ -636,7 +636,7 @@ void DAGCombiner::Run(bool RunningAfterLegalize) {
else {
assert(N->getValueType(0) == RV.getValueType() &&
N->getNumValues() == 1 && "Type mismatch");
- SDOperand OpV = RV;
+ SDValue OpV = RV;
DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
}
@@ -662,7 +662,7 @@ void DAGCombiner::Run(bool RunningAfterLegalize) {
DAG.setRoot(Dummy.getValue());
}
-SDOperand DAGCombiner::visit(SDNode *N) {
+SDValue DAGCombiner::visit(SDNode *N) {
switch(N->getOpcode()) {
default: break;
case ISD::TokenFactor: return visitTokenFactor(N);
@@ -726,12 +726,12 @@ SDOperand DAGCombiner::visit(SDNode *N) {
case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
}
- return SDOperand();
+ return SDValue();
}
-SDOperand DAGCombiner::combine(SDNode *N) {
+SDValue DAGCombiner::combine(SDNode *N) {
- SDOperand RV = visit(N);
+ SDValue RV = visit(N);
// If nothing happened, try a target-specific DAG combine.
if (RV.Val == 0) {
@@ -754,15 +754,15 @@ SDOperand DAGCombiner::combine(SDNode *N) {
if (RV.Val == 0 &&
SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
N->getNumValues() == 1) {
- SDOperand N0 = N->getOperand(0);
- SDOperand N1 = N->getOperand(1);
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
// Constant operands are canonicalized to RHS.
if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
- SDOperand Ops[] = { N1, N0 };
+ SDValue Ops[] = { N1, N0 };
SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
Ops, 2);
if (CSENode)
- return SDOperand(CSENode, 0);
+ return SDValue(CSENode, 0);
}
}
@@ -771,7 +771,7 @@ SDOperand DAGCombiner::combine(SDNode *N) {
/// getInputChainForNode - Given a node, return its input chain if it has one,
/// otherwise return a null sd operand.
-static SDOperand getInputChainForNode(SDNode *N) {
+static SDValue getInputChainForNode(SDNode *N) {
if (unsigned NumOps = N->getNumOperands()) {
if (N->getOperand(0).getValueType() == MVT::Other)
return N->getOperand(0);
@@ -781,10 +781,10 @@ static SDOperand getInputChainForNode(SDNode *N) {
if (N->getOperand(i).getValueType() == MVT::Other)
return N->getOperand(i);
}
- return SDOperand(0, 0);
+ return SDValue(0, 0);
}
-SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
+SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
// If N has two operands, where one has an input chain equal to the other,
// the 'other' chain is redundant.
if (N->getNumOperands() == 2) {
@@ -795,7 +795,7 @@ SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
}
SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
- SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
+ SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
SmallPtrSet<SDNode*, 16> SeenOps;
bool Changed = false; // If we should replace this token factor.
@@ -809,7 +809,7 @@ SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
// Check each of the operands.
for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
- SDOperand Op = TF->getOperand(i);
+ SDValue Op = TF->getOperand(i);
switch (Op.getOpcode()) {
case ISD::EntryToken:
@@ -841,7 +841,7 @@ SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
}
}
- SDOperand Result;
+ SDValue Result;
// If we've change things around then replace token factor.
if (Changed) {
@@ -861,22 +861,22 @@ SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
}
/// MERGE_VALUES can always be eliminated.
-SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) {
+SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
WorkListRemover DeadNodes(*this);
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
- DAG.ReplaceAllUsesOfValueWith(SDOperand(N, i), N->getOperand(i),
+ DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
&DeadNodes);
removeFromWorkList(N);
DAG.DeleteNode(N);
- return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
static
-SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
+SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) {
MVT VT = N0.getValueType();
- SDOperand N00 = N0.getOperand(0);
- SDOperand N01 = N0.getOperand(1);
+ SDValue N00 = N0.getOperand(0);
+ SDValue N01 = N0.getOperand(1);
ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
isa<ConstantSDNode>(N00.getOperand(1))) {
@@ -885,22 +885,22 @@ SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
return DAG.getNode(ISD::ADD, VT, N0, N1);
}
- return SDOperand();
+ return SDValue();
}
static
-SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
- SelectionDAG &DAG) {
+SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
+ SelectionDAG &DAG) {
MVT VT = N->getValueType(0);
unsigned Opc = N->getOpcode();
bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
- SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
- SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
+ SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
+ SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
ISD::CondCode CC = ISD::SETCC_INVALID;
if (isSlctCC)
CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
else {
- SDOperand CCOp = Slct.getOperand(0);
+ SDValue CCOp = Slct.getOperand(0);
if (CCOp.getOpcode() == ISD::SETCC)
CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
}