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-rw-r--r--lib/Target/Alpha/AlphaISelPattern.cpp20
-rw-r--r--lib/Target/Alpha/AlphaInstrInfo.td80
2 files changed, 65 insertions, 35 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index fc74a71bd0..7eaa3e4fc0 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -49,6 +49,7 @@ namespace {
addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass);
setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
+ setOperationAction(ISD::EXTLOAD , MVT::f32 , Promote);
setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
setOperationAction(ISD::ZEXTLOAD , MVT::i32 , Expand);
@@ -64,6 +65,7 @@ namespace {
setOperationAction(ISD::MEMSET , MVT::Other, Expand);
setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
+ //Doesn't work yet
setOperationAction(ISD::SETCC , MVT::f32, Promote);
computeRegisterProperties();
@@ -557,7 +559,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLE : Alpha::FCMOVGE; break;
case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQ : Alpha::FCMOVNE; break;
}
- BuildMI(BB, Opc, 3, Result).addReg(TV).addReg(FV).addReg(Tmp3);
+ BuildMI(BB, Opc, 3, Result).addReg(FV).addReg(TV).addReg(Tmp3);
return Result;
}
else
@@ -843,11 +845,11 @@ unsigned ISel::SelectExpr(SDOperand N) {
BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R30).addReg(Alpha::R30);
return Result;
- case ISD::ConstantPool:
- Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
- AlphaLowering.restoreGP(BB);
- BuildMI(BB, Alpha::LDQ_SYM, 1, Result).addConstantPoolIndex(Tmp1);
- return Result;
+// case ISD::ConstantPool:
+// Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
+// AlphaLowering.restoreGP(BB);
+// BuildMI(BB, Alpha::LDQ_SYM, 1, Result).addConstantPoolIndex(Tmp1);
+// return Result;
case ISD::FrameIndex:
BuildMI(BB, Alpha::LDA, 2, Result)
@@ -1393,8 +1395,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
}
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
+ //set up regs explicitly (helps Reg alloc)
+ BuildMI(BB, Alpha::BIS, 2, Alpha::R24).addReg(Tmp1).addReg(Tmp1);
+ BuildMI(BB, Alpha::BIS, 2, Alpha::R25).addReg(Tmp2).addReg(Tmp2);
AlphaLowering.restoreGP(BB);
- BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ BuildMI(BB, Opc, 2).addReg(Alpha::R24).addReg(Alpha::R25);
+ BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R27).addReg(Alpha::R27);
return Result;
case ISD::FP_TO_UINT:
diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index ea1697818c..6204539df1 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -79,13 +79,15 @@ let Uses = [R29, R28] in {
def STT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "stt $RA,$DISP">; //store double
}
+
+//RESULTS of these go to R27
let Uses = [R29],
- Defs = [R28, R29, R23, R24, R25, R27] in
+ Defs = [R28, R23, R24, R25, R27] in
{
- def REMQU : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "remqu $RA,$RB,$RC">; //unsigned remander
- def REMQ : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "remq $RA,$RB,$RC">; //signed remander
- def DIVQU : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "divqu $RA,$RB,$RC">; //unsigned division
- def DIVQ : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "divq $RA,$RB,$RC">; //signed division
+ def REMQU : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "remqu $RA,$RB,$$27">; //unsigned remander
+ def REMQ : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "remq $RA,$RB,$$27">; //signed remander
+ def DIVQU : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "divqu $RA,$RB,$$27">; //unsigned division
+ def DIVQ : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "divq $RA,$RB,$$27">; //signed division
}
//***********************
@@ -96,31 +98,52 @@ let Uses = [R29],
let isTwoAddress = 1 in {
//conditional moves, int
- def CMOVEQ : OForm< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "cmoveq $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND = zero
- def CMOVEQi : OFormL< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "cmoveq $RCOND,$L,$RDEST">; //CMOVE if RCOND = zero
- def CMOVGE : OForm< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "CMOVGE $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND >= zero
- def CMOVGEi : OFormL< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "CMOVGE $RCOND,$L,$RDEST">; //CMOVE if RCOND >= zero
- def CMOVGT : OForm< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "CMOVGT $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND > zero
- def CMOVGTi : OFormL< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "CMOVGT $RCOND,$L,$RDEST">; //CMOVE if RCOND > zero
- def CMOVLBC : OForm< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "CMOVLBC $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit clear
- def CMOVLBCi : OFormL< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "CMOVLBC $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit clear
- def CMOVLBS : OForm< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "CMOVLBS $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit set
- def CMOVLBSi : OFormL< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "CMOVLBS $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit set
- def CMOVLE : OForm< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "CMOVLE $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND <= zero
- def CMOVLEi : OFormL< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "CMOVLE $RCOND,$L,$RDEST">; //CMOVE if RCOND <= zero
- def CMOVLT : OForm< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "CMOVLT $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND < zero
- def CMOVLTi : OFormL< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "CMOVLT $RCOND,$L,$RDEST">; //CMOVE if RCOND < zero
- def CMOVNE : OForm< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "cmovne $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND != zero
- def CMOVNEi : OFormL< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero
+ def CMOVEQ : OForm< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ "cmoveq $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND = zero
+ def CMOVEQi : OFormL< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ "cmoveq $RCOND,$L,$RDEST">; //CMOVE if RCOND = zero
+ def CMOVGE : OForm< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ "CMOVGE $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND >= zero
+ def CMOVGEi : OFormL< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ "CMOVGE $RCOND,$L,$RDEST">; //CMOVE if RCOND >= zero
+ def CMOVGT : OForm< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ "CMOVGT $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND > zero
+ def CMOVGTi : OFormL< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ "CMOVGT $RCOND,$L,$RDEST">; //CMOVE if RCOND > zero
+ def CMOVLBC : OForm< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ "CMOVLBC $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit clear
+ def CMOVLBCi : OFormL< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ "CMOVLBC $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit clear
+ def CMOVLBS : OForm< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ "CMOVLBS $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit set
+ def CMOVLBSi : OFormL< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ "CMOVLBS $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit set
+ def CMOVLE : OForm< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ "CMOVLE $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND <= zero
+ def CMOVLEi : OFormL< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ "CMOVLE $RCOND,$L,$RDEST">; //CMOVE if RCOND <= zero
+ def CMOVLT : OForm< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ "CMOVLT $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND < zero
+ def CMOVLTi : OFormL< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ "CMOVLT $RCOND,$L,$RDEST">; //CMOVE if RCOND < zero
+ def CMOVNE : OForm< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
+ "cmovne $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND != zero
+ def CMOVNEi : OFormL< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
+ "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero
//conditional moves, fp
- def FCMOVEQ : FPForm<0x17, 0x02A, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmoveq $RCOND,$RSRC,$RDEST">; //FCMOVE if = zero
- def FCMOVGE : FPForm<0x17, 0x02D, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovge $RCOND,$RSRC,$RDEST">; //FCMOVE if >= zero
- def FCMOVGT : FPForm<0x17, 0x02F, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovge $RCOND,$RSRC,$RDEST">; //FCMOVE if > zero
- def FCMOVLE : FPForm<0x17, 0x02E, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovle $RCOND,$RSRC,$RDEST">; //FCMOVE if <= zero
- def FCMOVLT : FPForm<0x17, 0x02, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovlt $RCOND,$RSRC,$RDEST">; // FCMOVE if < zero
- def FCMOVNE : FPForm<0x17, 0x02B, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovne $RCOND,$RSRC,$RDEST">; //FCMOVE if != zero
-
+ def FCMOVEQ : FPForm<0x17, 0x02A, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
+ "fcmoveq $RCOND,$RSRC,$RDEST">; //FCMOVE if = zero
+ def FCMOVGE : FPForm<0x17, 0x02D, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
+ "fcmovge $RCOND,$RSRC,$RDEST">; //FCMOVE if >= zero
+ def FCMOVGT : FPForm<0x17, 0x02F, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
+ "fcmovgt $RCOND,$RSRC,$RDEST">; //FCMOVE if > zero
+ def FCMOVLE : FPForm<0x17, 0x02E, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
+ "fcmovle $RCOND,$RSRC,$RDEST">; //FCMOVE if <= zero
+ def FCMOVLT : FPForm<0x17, 0x02, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
+ "fcmovlt $RCOND,$RSRC,$RDEST">; // FCMOVE if < zero
+ def FCMOVNE : FPForm<0x17, 0x02B, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
+ "fcmovne $RCOND,$RSRC,$RDEST">; //FCMOVE if != zero
}
def ADDL : OForm< 0x10, 0x00, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "addl $RA,$RB,$RC">; //Add longword
@@ -218,6 +241,7 @@ def SLi : OFormL<0x12, 0x39, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "SLL $RA,$
def SRA : OForm< 0x12, 0x3C, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "SRA $RA,$RB,$RC">; //Shift right arithmetic
def SRAi : OFormL<0x12, 0x3C, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "SRA $RA,$L,$RC">; //Shift right arithmetic
def SRL : OForm< 0x12, 0x34, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "SRL $RA,$RB,$RC">; //Shift right logical
+
def SRLi : OFormL<0x12, 0x34, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "SRL $RA,$L,$RC">; //Shift right logical
def SUBL : OForm< 0x10, 0x09, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "SUBL $RA,$RB,$RC">; //Subtract longword
def SUBLi : OFormL<0x10, 0x09, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "SUBL $RA,$L,$RC">; //Subtract longword
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-05 23:13:10 +0000