diff options
Diffstat (limited to 'lib/Target')
22 files changed, 189 insertions, 196 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index f56043f5fd..9b6825d1b2 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -25,7 +25,6 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Support/Debug.h" diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 0415e19c0c..4d8a2372d0 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -24,12 +24,13 @@ #include "llvm/Constants.h" #include "llvm/Instruction.h" #include "llvm/Intrinsics.h" +#include "llvm/GlobalValue.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/VectorExtras.h" #include "llvm/Support/MathExtras.h" @@ -685,16 +686,16 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { Op.getValue(1), Sign); } Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand()); - if (DAG.getMachineFunction().liveout_empty()) - DAG.getMachineFunction().addLiveOut(ARM::R0); + if (DAG.getMachineFunction().getRegInfo().liveout_empty()) + DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); break; case 5: Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand()); Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); // If we haven't noted the R0+R1 are live out, do so now. - if (DAG.getMachineFunction().liveout_empty()) { - DAG.getMachineFunction().addLiveOut(ARM::R0); - DAG.getMachineFunction().addLiveOut(ARM::R1); + if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { + DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); + DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1); } break; } @@ -917,7 +918,7 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); SDOperand Root = Op.getOperand(0); std::vector<SDOperand> ArgValues; - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); static const unsigned GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 @@ -935,20 +936,20 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, SDOperand ArgValue; if (ObjGPRs == 1) { - unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); - MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); + RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); vRegs[NumGPRs] = VReg; ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); if (ObjectVT == MVT::f32) ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue); } else if (ObjGPRs == 2) { - unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); - MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); + RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); vRegs[NumGPRs] = VReg; ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); - VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); - MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); + VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); + RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); vRegs[NumGPRs+1] = VReg; SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); @@ -1002,7 +1003,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { }; MachineFunction &MF = DAG.getMachineFunction(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); MachineFrameInfo *MFI = MF.getFrameInfo(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); @@ -1019,8 +1020,8 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { SmallVector<SDOperand, 4> MemOps; for (; NumGPRs < 4; ++NumGPRs) { - unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); - MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); + RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 979410a58f..8328cef934 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -24,6 +24,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineLocation.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetMachine.h" @@ -1206,14 +1207,14 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, for (unsigned i = 0; CSRegs[i]; ++i) { unsigned Reg = CSRegs[i]; bool Spilled = false; - if (MF.isPhysRegUsed(Reg)) { + if (MF.getRegInfo().isPhysRegUsed(Reg)) { AFI->setCSRegisterIsSpilled(Reg); Spilled = true; CanEliminateFrame = false; } else { // Check alias registers too. for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { - if (MF.isPhysRegUsed(*Aliases)) { + if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { Spilled = true; CanEliminateFrame = false; } @@ -1286,7 +1287,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. // Spill LR as well so we can fold BX_RET to the registers restore (LDM). if (!LRSpilled && CS1Spilled) { - MF.setPhysRegUsed(ARM::LR); + MF.getRegInfo().setPhysRegUsed(ARM::LR); AFI->setCSRegisterIsSpilled(ARM::LR); NumGPRSpills++; UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), @@ -1298,7 +1299,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, // Darwin ABI requires FP to point to the stack slot that contains the // previous FP. if (STI.isTargetDarwin() || hasFP(MF)) { - MF.setPhysRegUsed(FramePtr); + MF.getRegInfo().setPhysRegUsed(FramePtr); NumGPRSpills++; } @@ -1312,7 +1313,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, unsigned Reg = UnspilledCS1GPRs[i]; // Don't spiil high register if the function is thumb if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) { - MF.setPhysRegUsed(Reg); + MF.getRegInfo().setPhysRegUsed(Reg); AFI->setCSRegisterIsSpilled(Reg); if (!isReservedReg(MF, Reg)) ExtraCSSpill = true; @@ -1322,7 +1323,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumbFunction()) { unsigned Reg = UnspilledCS2GPRs.front(); - MF.setPhysRegUsed(Reg); + MF.getRegInfo().setPhysRegUsed(Reg); AFI->setCSRegisterIsSpilled(Reg); if (!isReservedReg(MF, Reg)) ExtraCSSpill = true; @@ -1378,7 +1379,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, } if (Extras.size() && NumExtras == 0) { for (unsigned i = 0, e = Extras.size(); i != e; ++i) { - MF.setPhysRegUsed(Extras[i]); + MF.getRegInfo().setPhysRegUsed(Extras[i]); AFI->setCSRegisterIsSpilled(Extras[i]); } } else { @@ -1392,7 +1393,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, } if (ForceLRSpill) { - MF.setPhysRegUsed(ARM::LR); + MF.getRegInfo().setPhysRegUsed(ARM::LR); AFI->setCSRegisterIsSpilled(ARM::LR); AFI->setLRIsSpilledForFarJump(true); } @@ -1446,9 +1447,9 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { if (isThumb) { // Check if R3 is live in. It might have to be used as a scratch register. - for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end(); - I != E; ++I) { - if ((*I).first == ARM::R3) { + for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(), + E = MF.getRegInfo().livein_end(); I != E; ++I) { + if (I->first == ARM::R3) { AFI->setR3IsLiveIn(true); break; } diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 4b756b6582..0490f88bb4 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -18,7 +18,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetOptions.h" @@ -200,10 +200,9 @@ private: /// GOT address into a register. /// SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() { - MachineFunction* MF = BB->getParent(); unsigned GP = 0; - for(MachineFunction::livein_iterator ii = MF->livein_begin(), - ee = MF->livein_end(); ii != ee; ++ii) + for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), + ee = RegInfo->livein_end(); ii != ee; ++ii) if (ii->first == Alpha::R29) { GP = ii->second; break; @@ -216,10 +215,9 @@ SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() { /// getRASaveReg - Grab the return address /// SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() { - MachineFunction* MF = BB->getParent(); unsigned RA = 0; - for(MachineFunction::livein_iterator ii = MF->livein_begin(), - ee = MF->livein_end(); ii != ee; ++ii) + for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), + ee = RegInfo->livein_end(); ii != ee; ++ii) if (ii->first == Alpha::R26) { RA = ii->second; break; diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 295b456c0d..a37e8861bb 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -16,8 +16,9 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Constants.h" #include "llvm/Function.h" #include "llvm/Module.h" @@ -30,8 +31,8 @@ using namespace llvm; static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) { assert(RC->contains(PReg) && "Not the correct regclass!"); - unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC); - MF.addLiveIn(PReg, VReg); + unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); + MF.getRegInfo().addLiveIn(PReg, VReg); return VReg; } @@ -312,8 +313,8 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { ArgReg = Alpha::F0; } Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1)); - if (DAG.getMachineFunction().liveout_empty()) - DAG.getMachineFunction().addLiveOut(ArgReg); + if (DAG.getMachineFunction().getRegInfo().liveout_empty()) + DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg); break; } } diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index acd0c8bbfc..73e46fff1b 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -20,7 +20,6 @@ #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetOptions.h" diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 941cde1237..7893e677fb 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -20,8 +20,8 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/Constants.h" #include "llvm/Function.h" #include "llvm/Intrinsics.h" @@ -902,7 +902,7 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) { MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); SmallVector<SDOperand, 8> ArgValues; SDOperand Root = Op.getOperand(0); bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; @@ -932,8 +932,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) } case MVT::i8: if (!isVarArg && ArgRegIdx < NumArgRegs) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::R8CRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::R8CRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i8); ++ArgRegIdx; } else { @@ -942,8 +942,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) break; case MVT::i16: if (!isVarArg && ArgRegIdx < NumArgRegs) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::R16CRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::R16CRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i16); ++ArgRegIdx; } else { @@ -952,8 +952,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) break; case MVT::i32: if (!isVarArg && ArgRegIdx < NumArgRegs) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::R32CRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); ++ArgRegIdx; } else { @@ -962,8 +962,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) break; case MVT::i64: if (!isVarArg && ArgRegIdx < NumArgRegs) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::R64CRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::R64CRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); ++ArgRegIdx; } else { @@ -972,8 +972,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) break; case MVT::f32: if (!isVarArg && ArgRegIdx < NumArgRegs) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::R32FPRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32FPRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::f32); ++ArgRegIdx; } else { @@ -982,8 +982,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) break; case MVT::f64: if (!isVarArg && ArgRegIdx < NumArgRegs) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::R64FPRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::R64FPRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::f64); ++ArgRegIdx; } else { @@ -996,8 +996,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) case MVT::v8i16: case MVT::v16i8: if (!isVarArg && ArgRegIdx < NumArgRegs) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::VECREGRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); ++ArgRegIdx; } else { @@ -1037,8 +1037,8 @@ LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex) // result of va_next. SmallVector<SDOperand, 8> MemOps; for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) { - unsigned VReg = RegMap->createVirtualRegister(&SPU::GPRCRegClass); - MF.addLiveIn(ArgRegs[ArgRegIdx], VReg); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::GPRCRegClass); + RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg); SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); MemOps.push_back(Store); @@ -1294,9 +1294,9 @@ LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) { // If this is the first return lowered for this function, add the regs to the // liveout set for the function. - if (DAG.getMachineFunction().liveout_empty()) { + if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { for (unsigned i = 0; i != RVLocs.size(); ++i) - DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg()); + DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); } SDOperand Chain = Op.getOperand(0); @@ -1785,8 +1785,8 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { if (EltsFromV2 == 1 && monotonic) { // Compute mask and shuffle MachineFunction &MF = DAG.getMachineFunction(); - SSARegMap *RegMap = MF.getSSARegMap(); - unsigned VReg = RegMap->createVirtualRegister(&SPU::R32CRegClass); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Initialize temporary register to 0 SDOperand InitTempReg = @@ -1893,12 +1893,12 @@ static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) { // the wacky side case MVT::v8i16: { MachineFunction &MF = DAG.getMachineFunction(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); SDOperand Chain = Op.getOperand(0); SDOperand rA = Op.getOperand(0); SDOperand rB = Op.getOperand(1); - unsigned FSMBIreg = RegMap->createVirtualRegister(&SPU::VECREGRegClass); - unsigned HiProdReg = RegMap->createVirtualRegister(&SPU::VECREGRegClass); + unsigned FSMBIreg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); + unsigned HiProdReg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); SDOperand FSMBOp = DAG.getCopyToReg(Chain, FSMBIreg, @@ -1929,16 +1929,16 @@ static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) { // intermediate products. case MVT::v16i8: { MachineFunction &MF = DAG.getMachineFunction(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); SDOperand Chain = Op.getOperand(0); SDOperand rA = Op.getOperand(0); SDOperand rB = Op.getOperand(1); SDOperand c8 = DAG.getConstant(8, MVT::i8); SDOperand c16 = DAG.getConstant(16, MVT::i8); - unsigned FSMBreg_2222 = RegMap->createVirtualRegister(&SPU::VECREGRegClass); - unsigned LoProd_reg = RegMap->createVirtualRegister(&SPU::VECREGRegClass); - unsigned HiProd_reg = RegMap->createVirtualRegister(&SPU::VECREGRegClass); + unsigned FSMBreg_2222 = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); + unsigned LoProd_reg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); + unsigned HiProd_reg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); SDOperand LLProd = DAG.getNode(SPUISD::MPY, MVT::v8i16, @@ -2024,7 +2024,7 @@ static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) { static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); SDOperand A = Op.getOperand(0); SDOperand B = Op.getOperand(1); @@ -2033,11 +2033,11 @@ static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) { unsigned VRegBR, VRegC; if (VT == MVT::f32) { - VRegBR = RegMap->createVirtualRegister(&SPU::R32FPRegClass); - VRegC = RegMap->createVirtualRegister(&SPU::R32FPRegClass); + VRegBR = RegInfo.createVirtualRegister(&SPU::R32FPRegClass); + VRegC = RegInfo.createVirtualRegister(&SPU::R32FPRegClass); } else { - VRegBR = RegMap->createVirtualRegister(&SPU::VECREGRegClass); - VRegC = RegMap->createVirtualRegister(&SPU::VECREGRegClass); + VRegBR = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); + VRegC = RegInfo.createVirtualRegister(&SPU::VECREGRegClass); } // TODO: make sure we're feeding FPInterp the right arguments // Right now: fi B, frest(B) @@ -2066,18 +2066,6 @@ static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) { DAG.getCopyFromReg(AxBRcpl, VRegC, VT))))); } -// Expands double-precision FDIV -// Expects two doubles as inputs X and Y, does a floating point -// reciprocal estimate, and three iterations of Newton-Raphson -// to increase accuracy. -//static SDOperand LowerFDIVf64(SDOperand Op, SelectionDAG &DAG) { -// MachineFunction &MF = DAG.getMachineFunction(); -// SSARegMap *RegMap = MF.getSSARegMap(); -// -// SDOperand X = Op.getOperand(0); -// SDOperand Y = Op.getOperand(1); -//} - static SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) { unsigned VT = Op.getValueType(); SDOperand N = Op.getOperand(0); @@ -2365,9 +2353,9 @@ static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) { case MVT::i16: { MachineFunction &MF = DAG.getMachineFunction(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); - unsigned CNTB_reg = RegMap->createVirtualRegister(&SPU::R16CRegClass); + unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R16CRegClass); SDOperand N = Op.getOperand(0); SDOperand Elt0 = DAG.getConstant(0, MVT::i16); @@ -2397,10 +2385,10 @@ static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) { case MVT::i32: { MachineFunction &MF = DAG.getMachineFunction(); - SSARegMap *RegMap = MF.getSSARegMap(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); - unsigned CNTB_reg = RegMap->createVirtualRegister(&SPU::R32CRegClass); - unsigned SUM1_reg = RegMap->createVirtualRegister(&SPU::R32CRegClass); + unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); + unsigned SUM1_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); SDOperand N = Op.getOperand(0); SDOperand Elt0 = DAG.getConstant(0, MVT::i32); diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp index 9f8dbeede7..ec886d5680 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -27,6 +27,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/Target/TargetFrameInfo.h" @@ -670,15 +671,15 @@ void SPURegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, #if 0 // Save and clear the LR state. SPUFunctionInfo *FI = MF.getInfo<SPUFunctionInfo>(); - FI->setUsesLR(MF.isPhysRegUsed(LR)); + FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR)); #endif // Mark LR and SP unused, since the prolog spills them to stack and // we don't want anyone else to spill them for us. // // Also, unless R2 is really used someday, don't spill it automatically. - MF.setPhysRegUnused(SPU::R0); - MF.setPhysRegUnused(SPU::R1); - MF.setPhysRegUnused(SPU::R2); + MF.getRegInfo().setPhysRegUnused(SPU::R0); + MF.getRegInfo().setPhysRegUnused(SPU::R1); + MF.getRegInfo().setPhysRegUnused(SPU::R2); } void SPURegisterInfo::emitPrologue(MachineFunction &MF) const diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp index 0d9aeb3ac4..af31aaf555 100644 --- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -18,7 +18,6 @@ #include "IA64ISelLowering.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetOptions.h" diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index c02cd1bcc7..b6b6c256e4 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -18,7 +18,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Constants.h" #include "llvm/Function.h" using namespace llvm; @@ -148,9 +148,9 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { MachineFrameInfo *MFI = MF.getFrameInfo(); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); - GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); - SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); - RP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); + GP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); + SP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); + RP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); MachineBasicBlock& BB = MF.front(); @@ -182,10 +182,11 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // see intel ABI docs) case MVT::f64: //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]); - MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn + MF.getRegInfo().addLiveIn(args_FP[used_FPArgs]); + // mark this reg as liveIn // floating point args go into f8..f15 as-needed, the increment argVreg[count] = // is below..: - MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64)); + MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::f64)); // FP args go into f8..f15 as needed: (hence the ++) argPreg[count] = args_FP[used_FPArgs++]; argOpc[count] = IA64::FMOV; @@ -201,9 +202,10 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { case MVT::i32: case MVT::i64: //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]); - MF.addLiveIn(args_int[count]); // mark this register as liveIn + MF.getRegInfo().addLiveIn(args_int[count]); + // mark this register as liveIn argVreg[count] = - MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); + MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); argPreg[count] = args_int[count]; argOpc[count] = IA64::MOV; argt = newroot = @@ -232,7 +234,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { // Create a vreg to hold the output of (what will become) // the "alloc" instruction - VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); + VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR); // we create a PSEUDO_ALLOC (pseudo)instruction for now /* @@ -284,11 +286,11 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { case MVT::i16: case MVT::i32: case MVT::i64: - MF.addLiveOut(IA64::r8); + MF.getRegInfo().addLiveOut(IA64::r8); break; case MVT::f32: case MVT::f64: - MF.addLiveOut(IA64::F8); + MF.getRegInfo().addLiveOut(IA64::F8); break; } diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp index e00625c974..b570824594 100644 --- a/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/lib/Target/IA64/IA64RegisterInfo.cpp @@ -23,11 +23,11 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Support/CommandLine.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" using namespace llvm; @@ -328,8 +328,8 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const { IA64::r126, IA64::r127 }; unsigned numStackedGPRsUsed=0; - for(int i=0; i<96; i++) { - if(MF.isPhysRegUsed(RegsInOrder[i])) + for (int i=0; i != 96; i++) { + if (MF.getRegInfo().isPhysRegUsed(RegsInOrder[i])) |