diff options
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/X86/X86ISelDAGToDAG.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 9 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 1 |
3 files changed, 9 insertions, 4 deletions
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 35c5b42243..a7820795a1 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -1209,14 +1209,15 @@ SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { SDValue Tmp0, Tmp1, Tmp2, Tmp3; if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3)) return NULL; + SDValue LSI = Node->getOperand(4); // MemOperand AddToISelQueue(Tmp0); AddToISelQueue(Tmp1); AddToISelQueue(Tmp2); AddToISelQueue(Tmp3); AddToISelQueue(In2L); AddToISelQueue(In2H); + // For now, don't select the MemOperand object, we don't know how. AddToISelQueue(Chain); - SDValue LSI = CurDAG->getMemOperand(cast<MemSDNode>(In1)->getMemOperand()); const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, In2L, In2H, LSI, Chain }; return CurDAG->getTargetNode(Opc, MVT::i32, MVT::i32, MVT::Other, Ops, 8); } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 7f84d4c8a9..47a1ed70b1 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -6026,9 +6026,12 @@ SDValue X86TargetLowering::LowerATOMIC_BINARY_64(SDValue Op, assert(Node->getOperand(2).getNode()->getOpcode()==ISD::BUILD_PAIR); SDValue In2L = Node->getOperand(2).getNode()->getOperand(0); SDValue In2H = Node->getOperand(2).getNode()->getOperand(1); - SDValue Ops[] = { Chain, In1, In2L, In2H }; + // This is a generalized SDNode, not an AtomicSDNode, so it doesn't + // have a MemOperand. Pass the info through as a normal operand. + SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand()); + SDValue Ops[] = { Chain, In1, In2L, In2H, LSI }; SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); - SDValue Result = DAG.getNode(NewOp, Tys, Ops, 4); + SDValue Result = DAG.getNode(NewOp, Tys, Ops, 5); SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2); SDValue Vals[2] = { ResultVal, Result.getValue(2) }; @@ -6415,7 +6418,7 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, return nextMBB; } -// private utility function +// private utility function: 64 bit atomics on 32 bit host. MachineBasicBlock * X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, MachineBasicBlock *MBB, diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index de80bb2d45..d4bc05e603 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -2752,6 +2752,7 @@ def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val), let Constraints = "$val1 = $dst1, $val2 = $dst2", Defs = [EFLAGS, EAX, EBX, ECX, EDX], Uses = [EAX, EBX, ECX, EDX], + mayLoad = 1, mayStore = 1, usesCustomDAGSchedInserter = 1 in { def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2), (ins i64mem:$ptr, GR32:$val1, GR32:$val2), |