diff options
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelLowering.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/IA64/IA64ISelLowering.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/IA64/IA64ISelPattern.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/Sparc/SparcISelDAGToDAG.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/TargetSelectionDAG.td | 1 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 4 |
9 files changed, 13 insertions, 2 deletions
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index f6d8f36605..b9332890d6 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -81,6 +81,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) setOperationAction(ISD::CTTZ , MVT::i64 , Expand); setOperationAction(ISD::CTLZ , MVT::i64 , Expand); } + setOperationAction(ISD::BSWAP , MVT::i64, Expand); setOperationAction(ISD::ROTL , MVT::i64, Expand); setOperationAction(ISD::ROTR , MVT::i64, Expand); diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index 91d3f359b5..f56a02b1bc 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -82,6 +82,7 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM) setOperationAction(ISD::CTLZ , MVT::i64 , Expand); setOperationAction(ISD::ROTL , MVT::i64 , Expand); setOperationAction(ISD::ROTR , MVT::i64 , Expand); + setOperationAction(ISD::BSWAP, MVT::i64 , Expand); // mux @rev // Not implemented yet. setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp index 3aeb1598b6..3a1a413caf 100644 --- a/lib/Target/IA64/IA64ISelPattern.cpp +++ b/lib/Target/IA64/IA64ISelPattern.cpp @@ -98,6 +98,7 @@ namespace { setOperationAction(ISD::CTLZ , MVT::i64 , Expand); setOperationAction(ISD::ROTL , MVT::i64 , Expand); setOperationAction(ISD::ROTR , MVT::i64 , Expand); + setOperationAction(ISD::BSWAP, MVT::i64 , Expand); // mux @rev // FIXME: implement mulhs (xma.h) and mulhu (xma.hu) setOperationAction(ISD::MULHS , MVT::i64 , Expand); setOperationAction(ISD::MULHU , MVT::i64 , Expand); diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index d8c00dcb1a..7991821133 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -64,7 +64,8 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) setOperationAction(ISD::FSQRT, MVT::f32, Expand); } - // PowerPC does not have CTPOP or CTTZ + // PowerPC does not have BSWAP, CTPOP or CTTZ + setOperationAction(ISD::BSWAP, MVT::i32 , Expand); setOperationAction(ISD::CTPOP, MVT::i32 , Expand); setOperationAction(ISD::CTTZ , MVT::i32 , Expand); diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 7cfc68006b..85c69c6c09 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -150,6 +150,7 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) setOperationAction(ISD::CTLZ , MVT::i32, Expand); setOperationAction(ISD::ROTL , MVT::i32, Expand); setOperationAction(ISD::ROTR , MVT::i32, Expand); + setOperationAction(ISD::BSWAP, MVT::i32, Expand); setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); diff --git a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp index 7cfc68006b..85c69c6c09 100644 --- a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp +++ b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp @@ -150,6 +150,7 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) setOperationAction(ISD::CTLZ , MVT::i32, Expand); setOperationAction(ISD::ROTL , MVT::i32, Expand); setOperationAction(ISD::ROTR , MVT::i32, Expand); + setOperationAction(ISD::BSWAP, MVT::i32, Expand); setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td index 23abb10447..9537819aad 100644 --- a/lib/Target/TargetSelectionDAG.td +++ b/lib/Target/TargetSelectionDAG.td @@ -240,6 +240,7 @@ def xor : SDNode<"ISD::XOR" , SDTIntBinOp, [SDNPCommutative, SDNPAssociative]>; def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; +def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index d93ec3a537..a749380b86 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -109,6 +109,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); if (!X86DAGIsel) { + setOperationAction(ISD::BSWAP , MVT::i32 , Expand); setOperationAction(ISD::ROTL , MVT::i8 , Expand); setOperationAction(ISD::ROTR , MVT::i8 , Expand); setOperationAction(ISD::ROTL , MVT::i16 , Expand); @@ -116,6 +117,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::ROTL , MVT::i32 , Expand); setOperationAction(ISD::ROTR , MVT::i32 , Expand); } + setOperationAction(ISD::BSWAP , MVT::i16 , Expand); setOperationAction(ISD::READIO , MVT::i1 , Expand); setOperationAction(ISD::READIO , MVT::i8 , Expand); diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 291abd48e3..5427e249d0 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -518,7 +518,9 @@ def POP32r : I<0x58, AddRegFrm, let isTwoAddress = 1 in // R32 = bswap R32 def BSWAP32r : I<0xC8, AddRegFrm, - (ops R32:$dst, R32:$src), "bswap{l} $dst", []>, TB; + (ops R32:$dst, R32:$src), + "bswap{l} $dst", + [(set R32:$dst, (bswap R32:$src))]>, TB; def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8 (ops R8:$src1, R8:$src2), |