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-rw-r--r--lib/Target/ARM/ARM.h1
-rw-r--r--lib/Target/ARM/ARMConstantPoolValue.h2
-rw-r--r--lib/Target/Alpha/Alpha.h2
-rw-r--r--lib/Target/Alpha/AlphaInstrInfo.cpp1
-rw-r--r--lib/Target/CellSPU/SPU.h1
-rw-r--r--lib/Target/IA64/IA64.h2
-rw-r--r--lib/Target/IA64/IA64InstrInfo.cpp1
-rw-r--r--lib/Target/MSIL/MSILWriter.h1
-rw-r--r--lib/Target/Mips/Mips.h2
-rw-r--r--lib/Target/Mips/MipsMachineFunction.h1
-rw-r--r--lib/Target/PIC16/PIC16.h2
-rw-r--r--lib/Target/PowerPC/PPC.h3
-rw-r--r--lib/Target/PowerPC/PPCSubtarget.cpp1
-rw-r--r--lib/Target/Sparc/Sparc.h1
-rw-r--r--lib/Target/Sparc/SparcInstrInfo.cpp1
-rw-r--r--lib/Target/X86/X86.h2
-rw-r--r--lib/Target/X86/X86InstrInfo.cpp9
-rw-r--r--lib/Target/X86/X86InstrInfo.h4
-rw-r--r--lib/Target/X86/X86RegisterInfo.h2
-rw-r--r--lib/Target/X86/X86Subtarget.h1
20 files changed, 13 insertions, 27 deletions
diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h
index 4b26b2409c..0358230c66 100644
--- a/lib/Target/ARM/ARM.h
+++ b/lib/Target/ARM/ARM.h
@@ -15,7 +15,6 @@
#ifndef TARGET_ARM_H
#define TARGET_ARM_H
-#include <iosfwd>
#include <cassert>
namespace llvm {
diff --git a/lib/Target/ARM/ARMConstantPoolValue.h b/lib/Target/ARM/ARMConstantPoolValue.h
index 7b10565ba3..d2b9066dcc 100644
--- a/lib/Target/ARM/ARMConstantPoolValue.h
+++ b/lib/Target/ARM/ARMConstantPoolValue.h
@@ -15,7 +15,7 @@
#define LLVM_TARGET_ARM_CONSTANTPOOLVALUE_H
#include "llvm/CodeGen/MachineConstantPool.h"
-#include <ostream>
+#include <iosfwd>
namespace llvm {
diff --git a/lib/Target/Alpha/Alpha.h b/lib/Target/Alpha/Alpha.h
index f62270dd88..9af46d0c70 100644
--- a/lib/Target/Alpha/Alpha.h
+++ b/lib/Target/Alpha/Alpha.h
@@ -15,8 +15,6 @@
#ifndef TARGET_ALPHA_H
#define TARGET_ALPHA_H
-#include <iosfwd>
-
namespace llvm {
class AlphaTargetMachine;
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index bd6f2cf3e3..fa8224f113 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -15,6 +15,7 @@
#include "AlphaInstrInfo.h"
#include "AlphaGenInstrInfo.inc"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
using namespace llvm;
diff --git a/lib/Target/CellSPU/SPU.h b/lib/Target/CellSPU/SPU.h
index 776b9bfb08..a6a911067f 100644
--- a/lib/Target/CellSPU/SPU.h
+++ b/lib/Target/CellSPU/SPU.h
@@ -16,7 +16,6 @@
#define LLVM_TARGET_IBMCELLSPU_H
#include "llvm/Support/DataTypes.h"
-#include <iosfwd>
namespace llvm {
class SPUTargetMachine;
diff --git a/lib/Target/IA64/IA64.h b/lib/Target/IA64/IA64.h
index 1fe1488131..030a23382f 100644
--- a/lib/Target/IA64/IA64.h
+++ b/lib/Target/IA64/IA64.h
@@ -14,8 +14,6 @@
#ifndef TARGET_IA64_H
#define TARGET_IA64_H
-#include <iosfwd>
-
namespace llvm {
class IA64TargetMachine;
diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp
index a9dce85452..0a13c68abf 100644
--- a/lib/Target/IA64/IA64InstrInfo.cpp
+++ b/lib/Target/IA64/IA64InstrInfo.cpp
@@ -15,6 +15,7 @@
#include "IA64.h"
#include "IA64InstrBuilder.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/ADT/SmallVector.h"
#include "IA64GenInstrInfo.inc"
using namespace llvm;
diff --git a/lib/Target/MSIL/MSILWriter.h b/lib/Target/MSIL/MSILWriter.h
index c64ceeeff5..45f5579bfb 100644
--- a/lib/Target/MSIL/MSILWriter.h
+++ b/lib/Target/MSIL/MSILWriter.h
@@ -27,7 +27,6 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Support/Mangler.h"
-#include <algorithm>
#include <ios>
using namespace llvm;
diff --git a/lib/Target/Mips/Mips.h b/lib/Target/Mips/Mips.h
index 1dc53ca342..03f5a525ba 100644
--- a/lib/Target/Mips/Mips.h
+++ b/lib/Target/Mips/Mips.h
@@ -15,8 +15,6 @@
#ifndef TARGET_MIPS_H
#define TARGET_MIPS_H
-#include <iosfwd>
-
namespace llvm {
class MipsTargetMachine;
class FunctionPass;
diff --git a/lib/Target/Mips/MipsMachineFunction.h b/lib/Target/Mips/MipsMachineFunction.h
index fd5658c721..b95394ec81 100644
--- a/lib/Target/Mips/MipsMachineFunction.h
+++ b/lib/Target/Mips/MipsMachineFunction.h
@@ -14,6 +14,7 @@
#ifndef MIPS_MACHINE_FUNCTION_INFO_H
#define MIPS_MACHINE_FUNCTION_INFO_H
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/VectorExtras.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
diff --git a/lib/Target/PIC16/PIC16.h b/lib/Target/PIC16/PIC16.h
index f35acd5731..6850bd664b 100644
--- a/lib/Target/PIC16/PIC16.h
+++ b/lib/Target/PIC16/PIC16.h
@@ -15,8 +15,6 @@
#ifndef LLVM_TARGET_PIC16_H
#define LLVM_TARGET_PIC16_H
-#include <iosfwd>
-
namespace llvm {
class PIC16TargetMachine;
class FunctionPass;
diff --git a/lib/Target/PowerPC/PPC.h b/lib/Target/PowerPC/PPC.h
index 9a8e22e88d..773b9c169b 100644
--- a/lib/Target/PowerPC/PPC.h
+++ b/lib/Target/PowerPC/PPC.h
@@ -15,9 +15,6 @@
#ifndef LLVM_TARGET_POWERPC_H
#define LLVM_TARGET_POWERPC_H
-#include <iosfwd>
-
-
// GCC #defines PPC on Linux but we use it as our namespace name
#undef PPC
diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp
index e63368bd65..425d8e6195 100644
--- a/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -16,6 +16,7 @@
#include "llvm/Module.h"
#include "llvm/Target/TargetMachine.h"
#include "PPCGenSubtarget.inc"
+#include <cstdlib>
using namespace llvm;
#if defined(__APPLE__)
diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h
index 1096144e87..baac8f0159 100644
--- a/lib/Target/Sparc/Sparc.h
+++ b/lib/Target/Sparc/Sparc.h
@@ -15,7 +15,6 @@
#ifndef TARGET_SPARC_H
#define TARGET_SPARC_H
-#include <iosfwd>
#include <cassert>
namespace llvm {
diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp
index 8b07bcbabc..8601cbe4df 100644
--- a/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -15,6 +15,7 @@
#include "SparcSubtarget.h"
#include "Sparc.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "SparcGenInstrInfo.inc"
using namespace llvm;
diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h
index 0c2d3b36a2..135787b98a 100644
--- a/lib/Target/X86/X86.h
+++ b/lib/Target/X86/X86.h
@@ -15,8 +15,6 @@
#ifndef TARGET_X86_H
#define TARGET_X86_H
-#include <iosfwd>
-
namespace llvm {
class X86TargetMachine;
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index cb12a9d53c..9170c24ddb 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -18,6 +18,7 @@
#include "X86MachineFunctionInfo.h"
#include "X86Subtarget.h"
#include "X86TargetMachine.h"
+#include "llvm/DerivedTypes.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -1913,7 +1914,7 @@ bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
}
static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
- const SmallVector<MachineOperand,4> &MOs,
+ const SmallVectorImpl<MachineOperand> &MOs,
MachineInstr *MI, const TargetInstrInfo &TII) {
// Create the base instruction with the memory operand as the first part.
MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
@@ -1939,7 +1940,7 @@ static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
static MachineInstr *FuseInst(MachineFunction &MF,
unsigned Opcode, unsigned OpNo,
- const SmallVector<MachineOperand,4> &MOs,
+ const SmallVectorImpl<MachineOperand> &MOs,
MachineInstr *MI, const TargetInstrInfo &TII) {
MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
MachineInstrBuilder MIB(NewMI);
@@ -1961,7 +1962,7 @@ static MachineInstr *FuseInst(MachineFunction &MF,
}
static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
- const SmallVector<MachineOperand,4> &MOs,
+ const SmallVectorImpl<MachineOperand> &MOs,
MachineInstr *MI) {
MachineFunction &MF = *MI->getParent()->getParent();
MachineInstrBuilder MIB = BuildMI(MF, TII.get(Opcode));
@@ -1977,7 +1978,7 @@ static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
MachineInstr*
X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr *MI, unsigned i,
- const SmallVector<MachineOperand,4> &MOs) const{
+ const SmallVectorImpl<MachineOperand> &MOs) const{
const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
bool isTwoAddrFold = false;
unsigned NumOps = MI->getDesc().getNumOperands();
diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index 21c9a1f017..a75c5e64d1 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -17,7 +17,7 @@
#include "llvm/Target/TargetInstrInfo.h"
#include "X86.h"
#include "X86RegisterInfo.h"
-#include "llvm/ADT/IndexedMap.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/Target/TargetRegisterInfo.h"
namespace llvm {
@@ -447,7 +447,7 @@ private:
MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr* MI,
unsigned OpNum,
- const SmallVector<MachineOperand,4> &MOs) const;
+ const SmallVectorImpl<MachineOperand> &MOs) const;
};
} // End llvm namespace
diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h
index 25d7b07bad..b51a53327f 100644
--- a/lib/Target/X86/X86RegisterInfo.h
+++ b/lib/Target/X86/X86RegisterInfo.h
@@ -14,8 +14,6 @@
#ifndef X86REGISTERINFO_H
#define X86REGISTERINFO_H
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/SmallVector.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "X86GenRegisterInfo.h.inc"
diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h
index 646a953370..ded26e891e 100644
--- a/lib/Target/X86/X86Subtarget.h
+++ b/lib/Target/X86/X86Subtarget.h
@@ -15,7 +15,6 @@
#define X86SUBTARGET_H
#include "llvm/Target/TargetSubtarget.h"
-
#include <string>
namespace llvm {
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-04-26 16:57:33 +0000