15 files changed, 2305 insertions, 0 deletions

diff --git a/lib/Target/Alpha/Alpha.h b/lib/Target/Alpha/Alpha.h
new file mode 100644
index 0000000000..04daaffdbb
--- /dev/null
+++ b/lib/Target/Alpha/Alpha.h
@@ -0,0 +1,41 @@
+//===-- Alpha.h - Top-level interface for Alpha representation -*- C++ -*-//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+//
+// This file contains the entry points for global functions defined in the LLVM
+// Alpha back-end.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef TARGET_ALPHA_H
+#define TARGET_ALPHA_H
+
+#include <iosfwd>
+
+namespace llvm {
+
+  class FunctionPass;
+  class TargetMachine;
+
+  FunctionPass *createAlphaSimpleInstructionSelector(TargetMachine &TM);
+  FunctionPass *createAlphaCodePrinterPass(std::ostream &OS,
+                                             TargetMachine &TM);
+  FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
+
+} // end namespace llvm;
+
+// Defines symbolic names for Alpha registers.  This defines a mapping from
+// register name to register number.
+//
+#include "AlphaGenRegisterNames.inc"
+
+// Defines symbolic names for the Alpha instructions.
+//
+#include "AlphaGenInstrNames.inc"
+
+#endif
diff --git a/lib/Target/Alpha/Alpha.td b/lib/Target/Alpha/Alpha.td
new file mode 100644
index 0000000000..e48bea1e20
--- /dev/null
+++ b/lib/Target/Alpha/Alpha.td
@@ -0,0 +1,56 @@
+//===- Alpha.td - Describe the Alpha Target Machine ----*- tablegen -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+//
+//
+//===----------------------------------------------------------------------===//
+
+// Get the target-independent interfaces which we are implementing...
+//
+include "../Target.td"
+
+//Alpha is little endian
+
+//===----------------------------------------------------------------------===//
+// Register File Description
+//===----------------------------------------------------------------------===//
+
+include "AlphaRegisterInfo.td"
+
+//===----------------------------------------------------------------------===//
+// Instruction Descriptions
+//===----------------------------------------------------------------------===//
+
+include "AlphaInstrInfo.td"
+
+def AlphaInstrInfo : InstrInfo {
+  let PHIInst = PHI;
+
+  // Define how we want to layout our target-specific information field.
+ // let TSFlagsFields = [];
+ // let TSFlagsShifts = [];
+}
+
+def Alpha : Target {
+  // Pointers on Alpha are 64-bits in size.
+  let PointerType = i64;
+
+  let CalleeSavedRegisters = 
+	//saved regs
+	[R9, R10, R11, R12, R13, R14, 
+	//Frame pointer
+	R15, 
+	//return address
+	R26, 
+	//Stack Pointer
+	R30,
+         F2, F3, F4, F5, F6, F7, F8, F9];
+
+  // Pull in Instruction Info:
+  let InstructionSet = AlphaInstrInfo;
+}
diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp
new file mode 100644
index 0000000000..85feb9d531
--- /dev/null
+++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -0,0 +1,319 @@
+//===-- AlphaAsmPrinter.cpp - Alpha LLVM assembly writer --------------===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+//
+// This file contains a printer that converts from our internal representation
+// of machine-dependent LLVM code to GAS-format Alpha assembly language.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Alpha.h"
+#include "AlphaInstrInfo.h"
+#include "llvm/Constants.h"
+#include "llvm/DerivedTypes.h"
+#include "llvm/Module.h"
+#include "llvm/Assembly/Writer.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/CodeGen/AsmPrinter.h"
+
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/MRegisterInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
+
+#include "llvm/Support/Mangler.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/Support/CommandLine.h"
+#include <cctype>
+using namespace llvm;
+
+namespace {
+  Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
+
+  struct AlphaAsmPrinter : public AsmPrinter {
+
+    /// Unique incrementer for label values for referencing Global values.
+    ///
+    unsigned LabelNumber;
+ 
+     AlphaAsmPrinter(std::ostream &o, TargetMachine &tm) 
+      : AsmPrinter(o, tm), LabelNumber(0)
+    { }
+
+    /// We name each basic block in a Function with a unique number, so
+    /// that we can consistently refer to them later. This is cleared
+    /// at the beginning of each call to runOnMachineFunction().
+    ///
+    typedef std::map<const Value *, unsigned> ValueMapTy;
+    ValueMapTy NumberForBB;
+
+    virtual const char *getPassName() const {
+      return "Alpha Assembly Printer";
+    }
+    bool printInstruction(const MachineInstr *MI);
+    void printOp(const MachineOperand &MO, bool IsCallOp = false);
+    void printConstantPool(MachineConstantPool *MCP);
+    void printOperand(const MachineInstr *MI, int opNum, MVT::ValueType VT);
+    void printBaseOffsetPair (const MachineInstr *MI, int i, bool brackets=true);
+    void printMachineInstruction(const MachineInstr *MI);
+    bool runOnMachineFunction(MachineFunction &F);    
+    bool doInitialization(Module &M);
+    bool doFinalization(Module &M);
+  };
+} // end of anonymous namespace
+
+/// createAlphaCodePrinterPass - Returns a pass that prints the Alpha
+/// assembly code for a MachineFunction to the given output stream,
+/// using the given target machine description.  This should work
+/// regardless of whether the function is in SSA form.
+///
+FunctionPass *llvm::createAlphaCodePrinterPass (std::ostream &o,
+                                                  TargetMachine &tm) {
+  return new AlphaAsmPrinter(o, tm);
+}
+
+#include "AlphaGenAsmWriter.inc"
+
+void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum, MVT::ValueType VT)
+{
+  const MachineOperand &MO = MI->getOperand(opNum);
+  if (MO.getType() == MachineOperand::MO_MachineRegister) {
+    assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
+    O << LowercaseString(TM.getRegisterInfo()->get(MO.getReg()).Name);
+  } else if (MO.isImmediate()) {
+    O << MO.getImmedValue();
+  } else {
+    printOp(MO);
+  }
+}
+
+
+void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
+  const MRegisterInfo &RI = *TM.getRegisterInfo();
+  int new_symbol;
+  
+  switch (MO.getType()) {
+  case MachineOperand::MO_VirtualRegister:
+    if (Value *V = MO.getVRegValueOrNull()) {
+      O << "<" << V->getName() << ">";
+      return;
+    }
+    // FALLTHROUGH
+  case MachineOperand::MO_MachineRegister:
+  case MachineOperand::MO_CCRegister:
+    O << LowercaseString(RI.get(MO.getReg()).Name);
+    return;
+
+  case MachineOperand::MO_SignExtendedImmed:
+  case MachineOperand::MO_UnextendedImmed:
+    std::cerr << "printOp() does not handle immediate values\n";
+    abort();
+    return;
+
+  case MachineOperand::MO_PCRelativeDisp:
+    std::cerr << "Shouldn't use addPCDisp() when building PPC MachineInstrs";
+    abort();
+    return;
+    
+  case MachineOperand::MO_MachineBasicBlock: {
+    MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
+    O << "$LBB" << Mang->getValueName(MBBOp->getParent()->getFunction())
+      << "_" << MBBOp->getNumber() << "\t" << CommentString << " "
+      << MBBOp->getBasicBlock()->getName();
+    return;
+  }
+
+  case MachineOperand::MO_ConstantPoolIndex:
+    O << "$CPI" << CurrentFnName << "_" << MO.getConstantPoolIndex();
+    return;
+
+  case MachineOperand::MO_ExternalSymbol:
+    O << MO.getSymbolName();
+    return;
+
+  case MachineOperand::MO_GlobalAddress: 
+    //std::cerr << "Global Addresses?  Are you kidding?\n"
+    //abort();
+    O << Mang->getValueName(MO.getGlobal());
+    return;
+    
+  default:
+    O << "<unknown operand type: " << MO.getType() << ">";
+    return;
+  }
+}
+
+/// printMachineInstruction -- Print out a single Alpha MI to
+/// the current output stream.
+///
+void AlphaAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
+  ++EmittedInsts;
+  if (printInstruction(MI))
+    return; // Printer was automatically generated
+  
+  assert(0 && "Unhandled instruction in asm writer!");
+  abort();
+  return;
+}
+
+
+/// runOnMachineFunction - This uses the printMachineInstruction()
+/// method to print assembly for each instruction.
+///
+bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
+  setupMachineFunction(MF);
+  O << "\n\n";
+
+  if (CurrentFnName.compare("main") == 0)
+    {
+      O << "\n\n#HACK\n\t.text\n\t.ent __main\n__main:\n\tret $31,($26),1\n\t.end __main\n#ENDHACK\n\n";
+    }
+
+  // Print out constants referenced by the function
+  printConstantPool(MF.getConstantPool());
+
+  // Print out labels for the function.
+  O << "\t.text\n";
+  emitAlignment(2);
+  O << "\t.globl\t" << CurrentFnName << "\n";
+  O << "\t.ent\t" << CurrentFnName << "\n";
+
+  O << CurrentFnName << ":\n";
+
+  // Print out code for the function.
+  for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
+       I != E; ++I) {
+    // Print a label for the basic block.
+    O << "$LBB" << CurrentFnName << "_" << I->getNumber() << ":\t"
+      << CommentString << " " << I->getBasicBlock()->getName() << "\n";
+    for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
+         II != E; ++II) {
+      // Print the assembly for the instruction.
+      O << "\t";
+      printMachineInstruction(II);
+    }
+  }
+  ++LabelNumber;
+
+  O << "\t.end\t" << CurrentFnName << "\n";
+
+  // We didn't modify anything.
+  return false;
+}
+
+
+/// printConstantPool - Print to the current output stream assembly
+/// representations of the constants in the constant pool MCP. This is
+/// used to print out constants which have been "spilled to memory" by
+/// the code generator.
+///
+void AlphaAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
+  const std::vector<Constant*> &CP = MCP->getConstants();
+  const TargetData &TD = TM.getTargetData();
+ 
+  if (CP.empty()) return;
+
+  abort();
+//   for (unsigned i = 0, e = CP.size(); i != e; ++i) {
+//     O << "\t.section\t.rodata\n";
+//     emitAlignment(TD.getTypeAlignmentShift(CP[i]->getType()));
+//     O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t" << CommentString
+//       << *CP[i] << "\n";
+//     //emitGlobalConstant(CP[i]);
+//   }
+}
+
+bool AlphaAsmPrinter::doInitialization(Module &M)
+{
+  AsmPrinter::doInitialization(M);
+  O << "\t.arch ev56\n";
+  return false;
+}
+    
+
+// SwitchSection - Switch to the specified section of the executable if we are
+// not already in it!
+//
+static void SwitchSection(std::ostream &OS, std::string &CurSection,
+                          const char *NewSection) {
+  if (CurSection != NewSection) {
+    CurSection = NewSection;
+    if (!CurSection.empty())
+      OS << "\t" << NewSection << "\n";
+  }
+}
+
+bool AlphaAsmPrinter::doFinalization(Module &M) {
+  const TargetData &TD = TM.getTargetData();
+  std::string CurSection;
+  
+  for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I)
+    if (I->hasInitializer()) {   // External global require no code
+      O << "\n\n";
+      std::string name = Mang->getValueName(I);
+      Constant *C = I->getInitializer();
+      unsigned Size = TD.getTypeSize(C->getType());
+      unsigned Align = TD.getTypeAlignmentShift(C->getType());
+
+      if (C->isNullValue() && 
+          (I->hasLinkOnceLinkage() || I->hasInternalLinkage() ||
+           I->hasWeakLinkage() /* FIXME: Verify correct */)) {
+        SwitchSection(O, CurSection, ".data");
+        if (I->hasInternalLinkage())
+          O << "\t.local " << name << "\n";
+        
+        O << "\t.comm " << name << "," << TD.getTypeSize(C->getType())
+          << "," << (1 << Align);
+        O << "\t\t# ";
+        WriteAsOperand(O, I, true, true, &M);
+        O << "\n";
+      } else {
+        switch (I->getLinkage()) {
+        case GlobalValue::LinkOnceLinkage:
+        case GlobalValue::WeakLinkage:   // FIXME: Verify correct for weak.
+          // Nonnull linkonce -> weak
+          O << "\t.weak " << name << "\n";
+          SwitchSection(O, CurSection, "");
+          O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\",@progbits\n";
+          break;
+        case GlobalValue::AppendingLinkage:
+          // FIXME: appending linkage variables should go into a section of
+          // their name or something.  For now, just emit them as external.
+        case GlobalValue::ExternalLinkage:
+          // If external or appending, declare as a global symbol
+          O << "\t.globl " << name << "\n";
+          // FALL THROUGH
+        case GlobalValue::InternalLinkage:
+          if (C->isNullValue())
+            SwitchSection(O, CurSection, ".bss");
+          else
+            SwitchSection(O, CurSection, ".data");
+          break;
+        case GlobalValue::GhostLinkage:
+          std::cerr << "GhostLinkage cannot appear in X86AsmPrinter!\n";
+          abort();
+        }
+
+        emitAlignment(Align);
+        O << "\t.type " << name << ",@object\n";
+        O << "\t.size " << name << "," << Size << "\n";
+        O << name << ":\t\t\t\t# ";
+        WriteAsOperand(O, I, true, true, &M);
+        O << " = ";
+        WriteAsOperand(O, C, false, false, &M);
+        O << "\n";
+        emitGlobalConstant(C);
+      }
+    }
+
+  AsmPrinter::doFinalization(M);
+  return false;
+}
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
new file mode 100644
index 0000000000..4431d8f57f
--- /dev/null
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -0,0 +1,797 @@
+//===-- AlphaISelPattern.cpp - A pattern matching inst selector for Alpha -----===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+//
+// This file defines a pattern matching instruction selector for Alpha.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Alpha.h"
+//#include "X86InstrBuilder.h"
+#include "AlphaRegisterInfo.h"
+#include "llvm/Constants.h"                   // FIXME: REMOVE
+#include "llvm/Function.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/CodeGen/SSARegMap.h"
+#include "llvm/Target/TargetData.h"
+#include "llvm/Target/TargetLowering.h"
+#include "llvm/Support/MathExtras.h"
+#include "llvm/ADT/Statistic.h"
+#include <set>
+using namespace llvm;
+
+//===----------------------------------------------------------------------===//
+//  AlphaTargetLowering - Alpha Implementation of the TargetLowering interface
+namespace {
+  class AlphaTargetLowering : public TargetLowering {
+    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
+    unsigned GP; //GOT vreg
+  public:
+    AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
+      // Set up the TargetLowering object.
+      addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
+      addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass);
+
+      setOperationAction(ISD::EXTLOAD          , MVT::i1   , Expand);
+      setOperationAction(ISD::EXTLOAD          , MVT::i8   , Expand);
+      setOperationAction(ISD::EXTLOAD          , MVT::i16  , Expand);
+      setOperationAction(ISD::ZEXTLOAD         , MVT::i1   , Expand);
+      setOperationAction(ISD::ZEXTLOAD         , MVT::i8   , Expand);
+      setOperationAction(ISD::ZEXTLOAD         , MVT::i16  , Expand);
+      setOperationAction(ISD::ZEXTLOAD         , MVT::i32  , Expand);
+      setOperationAction(ISD::SEXTLOAD         , MVT::i1   , Expand);
+      setOperationAction(ISD::SEXTLOAD         , MVT::i8   , Expand);
+      setOperationAction(ISD::SEXTLOAD         , MVT::i16  , Expand);
+
+      computeRegisterProperties();
+      
+      //      setOperationUnsupported(ISD::MUL, MVT::i8);
+      //      setOperationUnsupported(ISD::SELECT, MVT::i1);
+      //      setOperationUnsupported(ISD::SELECT, MVT::i8);
+      
+      //      addLegalFPImmediate(+0.0); // FLD0
+      //      addLegalFPImmediate(+1.0); // FLD1
+      //      addLegalFPImmediate(-0.0); // FLD0/FCHS
+      //      addLegalFPImmediate(-1.0); // FLD1/FCHS
+    }
+
+    /// LowerArguments - This hook must be implemented to indicate how we should
+    /// lower the arguments for the specified function, into the specified DAG.
+    virtual std::vector<SDOperand>
+    LowerArguments(Function &F, SelectionDAG &DAG);
+
+    /// LowerCallTo - This hook lowers an abstract call to a function into an
+    /// actual call.
+    virtual std::pair<SDOperand, SDOperand>
+    LowerCallTo(SDOperand Chain, const Type *RetTy, SDOperand Callee,
+                ArgListTy &Args, SelectionDAG &DAG);
+
+    virtual std::pair<SDOperand, SDOperand>
+    LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
+
+    virtual std::pair<SDOperand,SDOperand>
+    LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
+                   const Type *ArgTy, SelectionDAG &DAG);
+
+    virtual std::pair<SDOperand, SDOperand>
+    LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
+                            SelectionDAG &DAG);
+
+    void restoreGP(MachineBasicBlock* BB)
+    {
+      BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
+    }
+  };
+}
+
+//http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
+
+//For now, just use variable size stack frame format
+
+//In a standard call, the first six items are passed in registers $16
+//- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
+//of argument-to-register correspondence.) The remaining items are
+//collected in a memory argument list that is a naturally aligned
+//array of quadwords. In a standard call, this list, if present, must
+//be passed at 0(SP).
+//7 ... n  	  	  	0(SP) ... (n-7)*8(SP)
+
+std::vector<SDOperand>
+AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) 
+{
+  std::vector<SDOperand> ArgValues;
+  
+  // //#define FP    $15
+  // //#define RA    $26
+  // //#define PV    $27
+  // //#define GP    $29
+  // //#define SP    $30
+  
+  //  assert(0 && "TODO");
+  MachineFunction &MF = DAG.getMachineFunction();
+  MachineFrameInfo *MFI = MF.getFrameInfo();
+
+  GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
+  MachineBasicBlock& BB = MF.front();
+
+  //Handle the return address
+  //BuildMI(&BB, Alpha::IDEF, 0, Alpha::R26);
+
+  unsigned args[] = {Alpha::R16, Alpha::R17, Alpha::R18, 
+		     Alpha::R19, Alpha::R20, Alpha::R21};
+  std::vector<unsigned> argVreg;
+
+  int count = 0;
+  for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I)
+    {
+      ++count;
+      assert(count <= 6 && "More than 6 args not supported");
+      assert(getValueType(I->getType()) != MVT::f64 && "No floats yet");
+      BuildMI(&BB, Alpha::IDEF, 0, args[count - 1]);
+      argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)));
+    }
+
+  BuildMI(&BB, Alpha::IDEF, 0, Alpha::R29);
+  BuildMI(&BB, Alpha::BIS, 2, GP).addReg(Alpha::R29).addReg(Alpha::R29);
+  count = 0;
+  for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I)
+    {
+      BuildMI(&BB, Alpha::BIS, 2, argVreg[count]).addReg(args[count]).addReg(args[count]);
+      
+      SDOperand argt, newroot;
+      switch (getValueType(I->getType()))
+	{
+	case MVT::i64:
+	  argt = newroot = DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot());
+	  break;
+	case MVT::i32:
+	  argt = newroot = DAG.getCopyFromReg(argVreg[count], MVT::i32, DAG.getRoot());
+	  break;
+	default:
+	  newroot = DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot());
+	  argt =  DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()), newroot);
+	}
+      DAG.setRoot(newroot.getValue(1));
+      ArgValues.push_back(argt);
+      ++count;
+    }
+  return ArgValues;
+}
+
+std::pair<SDOperand, SDOperand>
+AlphaTargetLowering::LowerCallTo(SDOperand Chain,
+				 const Type *RetTy, SDOperand Callee,
+				 ArgListTy &Args, SelectionDAG &DAG) {
+  int NumBytes = 0;
+  Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
+		      DAG.getConstant(NumBytes, getPointerTy()));
+  std::vector<SDOperand> args_to_use;
+  for (unsigned i = 0, e = Args.size(); i != e; ++i)
+    {
+      switch (getValueType(Args[i].second)) {
+      default: assert(0 && "Unexpected ValueType for argument!");
+      case MVT::i1:
+      case MVT::i8:
+      case MVT::i16:
+      case MVT::i32:
+	// Promote the integer to 64 bits.  If the input type is signed use a
+	// sign extend, otherwise use a zero extend.
+	if (Args[i].second->isSigned())
+	  Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
+	else
+	  Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
+	break;
+      case MVT::i64:
+	break;
+      }
+      args_to_use.push_back(Args[i].first);
+    }
+
+  std::vector<MVT::ValueType> RetVals;
+  MVT::ValueType RetTyVT = getValueType(RetTy);
+  if (RetTyVT != MVT::isVoid)
+    RetVals.push_back(RetTyVT);
+  RetVals.push_back(MVT::Other);
+
+  SDOperand TheCall = SDOperand(DAG.getCall(RetVals, Chain, Callee, args_to_use), 0);
+  Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
+  Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
+                      DAG.getConstant(NumBytes, getPointerTy()));
+   return std::make_pair(TheCall, Chain);
+}
+
+std::pair<SDOperand, SDOperand>
+AlphaTargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
+  //vastart just returns the address of the VarArgsFrameIndex slot.
+  return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64), Chain);
+}
+
+std::pair<SDOperand,SDOperand> AlphaTargetLowering::
+LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
+                const Type *ArgTy, SelectionDAG &DAG) {
+  abort();
+}
+               
+
+std::pair<SDOperand, SDOperand> AlphaTargetLowering::
+LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
+                        SelectionDAG &DAG) {
+  abort();
+}
+
+
+
+
+
+namespace {
+
+  //===--------------------------------------------------------------------===//
+  /// ISel - Alpha specific code to select Alpha machine instructions for
+  /// SelectionDAG operations.
+  ///
+  class ISel : public SelectionDAGISel {
+
+    /// AlphaLowering - This object fully describes how to lower LLVM code to an
+    /// Alpha-specific SelectionDAG.
+    AlphaTargetLowering AlphaLowering;
+
+
+    /// ExprMap - As shared expressions are codegen'd, we keep track of which
+    /// vreg the value is produced in, so we only emit one copy of each compiled
+    /// tree.
+    std::map<SDOperand, unsigned> ExprMap;
+    std::set<SDOperand> LoweredTokens;
+
+  public:
+    ISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), AlphaLowering(TM) {
+    }
+
+    /// InstructionSelectBasicBlock - This callback is invoked by
+    /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
+    virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
+      // Codegen the basic block.
+      Select(DAG.getRoot());
+
+      // Clear state used for selection.
+      ExprMap.clear();
+      LoweredTokens.clear();
+    }
+
+    unsigned SelectExpr(SDOperand N);
+    void Select(SDOperand N);
+  };
+}
+
+unsigned ISel::SelectExpr(SDOperand N) {
+  unsigned Result;
+  unsigned Tmp1, Tmp2, Tmp3;
+  unsigned Opc = 0;
+
+  SDNode *Node = N.Val;
+
+  unsigned &Reg = ExprMap[N];
+  if (Reg) return Reg;
+
+  if (N.getOpcode() != ISD::CALL)
+    Reg = Result = (N.getValueType() != MVT::Other) ?
+      MakeReg(N.getValueType()) : 1;
+  else {
+    // If this is a call instruction, make sure to prepare ALL of the result
+    // values as well as the chain.
+    if (Node->getNumValues() == 1)
+      Reg = Result = 1;  // Void call, just a chain.
+    else {
+      Result = MakeReg(Node->getValueType(0));
+      ExprMap[N.getValue(0)] = Result;
+      for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
+        ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
+      ExprMap[SDOperand(Node, Node->getNumValues()-1)] = 1;
+    }
+  }
+
+  switch (N.getOpcode()) {
+  default:
+    Node->dump();
+    assert(0 && "Node not handled!\n");
+ 
+  case ISD::FrameIndex:
+    Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
+    BuildMI(BB, Alpha::LDA, 2, Result).addImm(Tmp1 * 8).addReg(Alpha::R30);
+    return Result;
+  
+  case ISD::EXTLOAD:
+  case ISD::SEXTLOAD:
+    // Make sure we generate both values.
+    if (Result != 1)
+      ExprMap[N.getValue(1)] = 1;   // Generate the token
+    else
+      Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
+    
+    Select(Node->getOperand(0)); // chain
+    Tmp1 = SelectExpr(Node->getOperand(1));
+    switch(Node->getValueType(0)) {
+    default: assert(0 && "Unknown type to sign extend to.");
+    case MVT::i64:
+      switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
+      default:
+        assert(0 && "Bad sign extend!");
+      case MVT::i32:
+	BuildMI(BB, Alpha::LDL, 2, Result).addImm(0).addReg(Tmp1);
+        break;
+      case MVT::i16:
+	BuildMI(BB, Alpha::LDW, 2, Result).addImm(0).addReg(Tmp1);
+        break;
+      case MVT::i8:
+	BuildMI(BB, Alpha::LDB, 2, Result).addImm(0).addReg(Tmp1);
+        break;
+      }
+      break;
+    }
+    return Result;
+
+  case ISD::GlobalAddress:
+    AlphaLowering.restoreGP(BB);
+    BuildMI(BB, Alpha::LOAD_ADDR, 1, Result)
+      .addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal());
+    return Result;
+
+  case ISD::CALL:
+    {
+      Select(N.getOperand(0));
+
+      // The chain for this call is now lowered.
+      ExprMap.insert(std::make_pair(N.getValue(Node->getNumValues()-1), 1));
+      
+      //grab the arguments
+      std::vector<unsigned> argvregs;
+      assert(Node->getNumOperands() < 8 && "Only 6 args supported");
+      for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
+      {
+	argvregs.push_back(SelectExpr(N.getOperand(i)));
+      }
+      for(int i = 0, e = argvregs.size(); i < e; ++i)
+      {
+	unsigned args[] = {Alpha::R16, Alpha::R17, Alpha::R18, 
+			   Alpha::R19, Alpha::R20, Alpha::R21};
+	
+	BuildMI(BB, Alpha::BIS, 2, args[i]).addReg(argvregs[i]).addReg(argvregs[i]);
+      }
+
+    //build the right kind of call
+    if (GlobalAddressSDNode *GASD =
+               dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) 
+      {
+	Select(N.getOperand(0));
+	AlphaLowering.restoreGP(BB);
+	BuildMI(BB, Alpha::CALL, 1).addGlobalAddress(GASD->getGlobal(),true);
+      }
+    else if (ExternalSymbolSDNode *ESSDN =
+	     dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) 
+      {
+	Select(N.getOperand(0));
+	AlphaLowering.restoreGP(BB);
+	BuildMI(BB, Alpha::CALL, 0).addExternalSymbol(ESSDN->getSymbol(), true);
+      } 
+    else {
+      Select(N.getOperand(0));
+      Tmp1 = SelectExpr(N.getOperand(1));
+      BuildMI(BB, Alpha::CALL, 1).addReg(Tmp1);
+      AlphaLowering.restoreGP(BB);
+    }
+
+    //push the result into a virtual register
+    //    if (Result != 1)
+    //      BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
+
+    switch (Node->getValueType(0)) {
+    default: assert(0 && "Unknown value type for call result!");
+    case MVT::Other: return 1;
+    case MVT::i1:
+    case MVT::i8:
+    case MVT::i16:
+    case MVT::i32:
+    case MVT::i64:
+      BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
+    break;
+    }
+    return Result+N.ResNo;
+    }    
+  
+  case ISD::SIGN_EXTEND:
+    {
+      std::cerr << "DestT: " << N.getValueType() << "\n";
+      std::cerr << "SrcT: " << N.getOperand(0).getValueType() << "\n";
+      assert(0 && "Sign Extend not there yet");
+      return Result;
+    }
+  case ISD::SIGN_EXTEND_INREG:
+    {
+      Tmp1 = SelectExpr(N.getOperand(0));
+      MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);
+      std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
+      switch(MVN->getExtraValueType())
+	{
+	default:
+	  assert(0 && "Sign Extend InReg not there yet");
+	  break;
+	case MVT::i32:
+	  {
+	    Tmp2 = MakeReg(MVT::i64);
+	    unsigned Tmp3 = MakeReg(MVT::i64);
+	    BuildMI(BB, Alpha::LOAD_IMM, 1, Tmp2).addImm(16);
+	    BuildMI(BB, Alpha::SL, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
+	    BuildMI(BB, Alpha::SRA, 2, Result).addReg(Tmp3).addReg(Tmp2);
+	    break;
+	  }
+	case MVT::i16:
+	  BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Tmp1);
+	  break;
+	case MVT::i8:
+	  BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1);
+	  break;
+	}
+      return Result;
+    }
+  case ISD::ZERO_EXTEND_INREG:
+    {
+      Tmp1 = SelectExpr(N.getOperand(0));
+      MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);
+      std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
+      switch(MVN->getExtraValueType())
+	{
+	default:
+	  assert(0 && "Zero Extend InReg not there yet");
+	  break;
+	case MVT::i32:
+	  {
+	    Tmp2 = MakeReg(MVT::i64);
+	    BuildMI(BB, Alpha::LOAD_IMM, 1, Tmp2).addImm(0xf0);
+	    BuildMI(BB, Alpha::ZAP, 2, Result).addReg(Tmp1).addReg(Tmp2);
+	    break;
+	  }
+	case MVT::i16:
+	    Tmp2 = MakeReg(MVT::i64);
+	    BuildMI(BB, Alpha::LOAD_IMM, 1, Tmp2).addImm(0xfc);
+	    BuildMI(BB, Alpha::ZAP, 2, Result).addReg(Tmp1).addReg(Tmp2);
+	    break;
+	case MVT::i8:
+	    Tmp2 = MakeReg(MVT::i64);
+	    BuildMI(BB, Alpha::LOAD_IMM, 1, Tmp2).addImm(0xfe);
+	    BuildMI(BB, Alpha::ZAP, 2, Result).addReg(Tmp1).addReg(Tmp2);
+	    break;
+	}
+      return Result;
+    }
+    
+  case ISD::SETCC:
+    Tmp1 = SelectExpr(N.getOpe