diff options
Diffstat (limited to 'lib/Target')
71 files changed, 332 insertions, 296 deletions
diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h index 0e654d8e64..471c212583 100644 --- a/lib/Target/ARM/ARM.h +++ b/lib/Target/ARM/ARM.h @@ -15,6 +15,7 @@ #ifndef TARGET_ARM_H #define TARGET_ARM_H +#include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetMachine.h" #include <cassert> @@ -51,7 +52,7 @@ namespace ARMCC { inline static CondCodes getOppositeCondition(CondCodes CC){ switch (CC) { - default: assert(0 && "Unknown condition code"); + default: LLVM_UNREACHABLE("Unknown condition code"); case EQ: return NE; case NE: return EQ; case HS: return LO; @@ -72,7 +73,7 @@ namespace ARMCC { inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { switch (CC) { - default: assert(0 && "Unknown condition code"); + default: LLVM_UNREACHABLE("Unknown condition code"); case ARMCC::EQ: return "eq"; case ARMCC::NE: return "ne"; case ARMCC::HS: return "hs"; diff --git a/lib/Target/ARM/ARMAddressingModes.h b/lib/Target/ARM/ARMAddressingModes.h index 6b90b73d13..40e3e8690f 100644 --- a/lib/Target/ARM/ARMAddressingModes.h +++ b/lib/Target/ARM/ARMAddressingModes.h @@ -15,6 +15,7 @@ #define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H #include "llvm/CodeGen/SelectionDAGNodes.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include <cassert> @@ -37,7 +38,7 @@ namespace ARM_AM { static inline const char *getShiftOpcStr(ShiftOpc Op) { switch (Op) { - default: assert(0 && "Unknown shift opc!"); + default: LLVM_UNREACHABLE("Unknown shift opc!"); case ARM_AM::asr: return "asr"; case ARM_AM::lsl: return "lsl"; case ARM_AM::lsr: return "lsr"; @@ -70,7 +71,7 @@ namespace ARM_AM { static inline const char *getAMSubModeStr(AMSubMode Mode) { switch (Mode) { - default: assert(0 && "Unknown addressing sub-mode!"); + default: LLVM_UNREACHABLE("Unknown addressing sub-mode!"); case ARM_AM::ia: return "ia"; case ARM_AM::ib: return "ib"; case ARM_AM::da: return "da"; @@ -80,7 +81,7 @@ namespace ARM_AM { static inline const char *getAMSubModeAltStr(AMSubMode Mode, bool isLD) { switch (Mode) { - default: assert(0 && "Unknown addressing sub-mode!"); + default: LLVM_UNREACHABLE("Unknown addressing sub-mode!"); case ARM_AM::ia: return isLD ? "fd" : "ea"; case ARM_AM::ib: return isLD ? "ed" : "fa"; case ARM_AM::da: return isLD ? "fa" : "ed"; diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index d7ba73c3e4..9bca6a787d 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -23,6 +23,7 @@ #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/Target/TargetAsmInfo.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/ErrorHandling.h" using namespace llvm; static cl::opt<bool> @@ -433,8 +434,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { return 0; switch (MI->getOpcode()) { default: - assert(0 && "Unknown or unset size field for instr!"); - break; + LLVM_UNREACHABLE("Unknown or unset size field for instr!"); case TargetInstrInfo::IMPLICIT_DEF: case TargetInstrInfo::DECLARE: case TargetInstrInfo::DBG_LABEL: diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 377de19456..c93473d62e 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -707,12 +707,12 @@ unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const { } unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { - assert(0 && "What is the exception register"); + LLVM_UNREACHABLE("What is the exception register"); return 0; } unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { - assert(0 && "What is the exception handler register"); + LLVM_UNREACHABLE("What is the exception handler register"); return 0; } diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp index 34c9d70e69..1f2376e638 100644 --- a/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -24,6 +24,7 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/Statistic.h" @@ -448,7 +449,7 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn, Bits = 8; // Taking the address of a CP entry. break; } - assert(0 && "Unknown addressing mode for CP reference!"); + LLVM_UNREACHABLE("Unknown addressing mode for CP reference!"); case ARMII::AddrMode1: // AM1: 8 bits << 2 Bits = 8; Scale = 4; // Taking the address of a CP entry. diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 5c604a92cf..dec7a72bed 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -470,7 +470,7 @@ unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const { /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { switch (CC) { - default: assert(0 && "Unknown condition code!"); + default: LLVM_UNREACHABLE("Unknown condition code!"); case ISD::SETNE: return ARMCC::NE; case ISD::SETEQ: return ARMCC::EQ; case ISD::SETGT: return ARMCC::GT; @@ -492,7 +492,7 @@ static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool Invert = false; CondCode2 = ARMCC::AL; switch (CC) { - default: assert(0 && "Unknown FP condition!"); + default: LLVM_UNREACHABLE("Unknown FP condition!"); case ISD::SETEQ: case ISD::SETOEQ: CondCode = ARMCC::EQ; break; case ISD::SETGT: @@ -661,7 +661,7 @@ CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC, bool Return) const { switch (CC) { default: - assert(0 && "Unsupported calling convention"); + LLVM_UNREACHABLE("Unsupported calling convention"); case CallingConv::C: case CallingConv::Fast: // Use target triple & subtarget features to do actual dispatch. @@ -745,7 +745,7 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, } switch (VA.getLocInfo()) { - default: assert(0 && "Unknown loc info!"); + default: LLVM_UNREACHABLE("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::BCvt: Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val); @@ -858,7 +858,7 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { // Promote the value if needed. switch (VA.getLocInfo()) { - default: assert(0 && "Unknown loc info!"); + default: LLVM_UNREACHABLE("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); @@ -1060,7 +1060,7 @@ SDValue ARMTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { SDValue Arg = Op.getOperand(realRVLocIdx*2+1); switch (VA.getLocInfo()) { - default: assert(0 && "Unknown loc info!"); + default: LLVM_UNREACHABLE("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::BCvt: Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg); @@ -1442,7 +1442,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { // to 32 bits. Insert an assert[sz]ext to capture this, then // truncate to the right size. switch (VA.getLocInfo()) { - default: assert(0 && "Unknown loc info!"); + default: LLVM_UNREACHABLE("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::BCvt: ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); @@ -2006,7 +2006,7 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { if (Op.getOperand(1).getValueType().isFloatingPoint()) { switch (SetCCOpcode) { - default: assert(0 && "Illegal FP comparison"); break; + default: LLVM_UNREACHABLE("Illegal FP comparison"); break; case ISD::SETUNE: case ISD::SETNE: Invert = true; // Fallthrough case ISD::SETOEQ: @@ -2045,7 +2045,7 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { } else { // Integer comparisons. switch (SetCCOpcode) { - default: assert(0 && "Illegal integer comparison"); break; + default: LLVM_UNREACHABLE("Illegal integer comparison"); break; case ISD::SETNE: Invert = true; case ISD::SETEQ: Opc = ARMISD::VCEQ; break; case ISD::SETLT: Swap = true; @@ -2149,7 +2149,7 @@ static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef, } default: - assert(0 && "unexpected size for isVMOVSplat"); + LLVM_UNREACHABLE("unexpected size for isVMOVSplat"); break; } @@ -2191,7 +2191,7 @@ static SDValue BuildSplat(SDValue Val, MVT VT, SelectionDAG &DAG, DebugLoc dl) { case 16: CanonicalVT = MVT::v4i16; break; case 32: CanonicalVT = MVT::v2i32; break; case 64: CanonicalVT = MVT::v1i64; break; - default: assert(0 && "unexpected splat element type"); break; + default: LLVM_UNREACHABLE("unexpected splat element type"); break; } } else { assert(VT.is128BitVector() && "unknown splat vector size"); @@ -2200,7 +2200,7 @@ static SDValue BuildSplat(SDValue Val, MVT VT, SelectionDAG &DAG, DebugLoc dl) { case 16: CanonicalVT = MVT::v8i16; break; case 32: CanonicalVT = MVT::v4i32; break; case 64: CanonicalVT = MVT::v2i64; break; - default: assert(0 && "unexpected splat element type"); break; + default: LLVM_UNREACHABLE("unexpected splat element type"); break; } } @@ -2303,7 +2303,7 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) { switch (N->getOpcode()) { default: - assert(0 && "Don't know how to custom expand this!"); + LLVM_UNREACHABLE("Don't know how to custom expand this!"); return; case ISD::BIT_CONVERT: Results.push_back(ExpandBIT_CONVERT(N, DAG)); @@ -2628,7 +2628,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { LLVM_UNREACHABLE("invalid shift count for narrowing vector shift intrinsic"); default: - assert(0 && "unhandled vector shift"); + LLVM_UNREACHABLE("unhandled vector shift"); } switch (IntNo) { @@ -2720,7 +2720,7 @@ static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, int64_t Cnt; switch (N->getOpcode()) { - default: assert(0 && "unexpected shift opcode"); + default: LLVM_UNREACHABLE("unexpected shift opcode"); case ISD::SHL: if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) @@ -2763,7 +2763,7 @@ static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, unsigned Opc = 0; switch (N->getOpcode()) { - default: assert(0 && "unexpected opcode"); + default: LLVM_UNREACHABLE("unexpected opcode"); case ISD::SIGN_EXTEND: Opc = ARMISD::VGETLANEs; break; diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 6fa05fc108..977e621b65 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -338,7 +338,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { bool rev = false; bool inv = false; switch(CC) { - default: DEBUG(N->dump(CurDAG)); assert(0 && "Unknown FP comparison!"); + default: DEBUG(N->dump(CurDAG)); LLVM_UNREACHABLE("Unknown FP comparison!"); case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ: Opc = Alpha::CMPTEQ; break; case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: @@ -472,7 +472,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { } else if (TypeOperands[i] == MVT::f64) { Opc = Alpha::STT; } else - assert(0 && "Unknown operand"); + LLVM_UNREACHABLE("Unknown operand"); SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8), CurDAG->getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64), @@ -489,7 +489,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { CallOperands[i], InFlag); InFlag = Chain.getValue(1); } else - assert(0 && "Unknown operand"); + LLVM_UNREACHABLE("Unknown operand"); } // Finally, once everything is in registers to pass to the call, emit the @@ -512,7 +512,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { std::vector<SDValue> CallResults; switch (N->getValueType(0).getSimpleVT()) { - default: assert(0 && "Unexpected ret value!"); + default: LLVM_UNREACHABLE("Unexpected ret value!"); case MVT::Other: break; case MVT::i64: Chain = CurDAG->getCopyFromReg(Chain, dl, diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 49fb262b5a..289353631e 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -380,7 +380,7 @@ AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, for (unsigned i = 0, e = Args.size(); i != e; ++i) { switch (getValueType(Args[i].Ty).getSimpleVT()) { - default: assert(0 && "Unexpected ValueType for argument!"); + default: LLVM_UNREACHABLE("Unexpected ValueType for argument!"); case MVT::i1: case MVT::i8: case MVT::i16: @@ -476,7 +476,7 @@ void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain, SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); switch (Op.getOpcode()) { - default: assert(0 && "Wasn't expecting to be able to lower this!"); + default: LLVM_UNREACHABLE("Wasn't expecting to be able to lower this!"); case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsBase, VarArgsOffset); @@ -527,7 +527,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { return Lo; } case ISD::GlobalTLSAddress: - assert(0 && "TLS not implemented for Alpha."); + LLVM_UNREACHABLE("TLS not implemented for Alpha."); case ISD::GlobalAddress: { GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); GlobalValue *GV = GSDN->getGlobal(); diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 62b5d4c301..139a4db655 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -332,7 +332,7 @@ static unsigned AlphaRevCondCode(unsigned Opcode) { case Alpha::FBLE: return Alpha::FBGT; case Alpha::FBLT: return Alpha::FBGE; default: - assert(0 && "Unknown opcode"); + LLVM_UNREACHABLE("Unknown opcode"); } return 0; // Not reached } diff --git a/lib/Target/Alpha/AlphaJITInfo.cpp b/lib/Target/Alpha/AlphaJITInfo.cpp index c62ab75523..8919dc0492 100644 --- a/lib/Target/Alpha/AlphaJITInfo.cpp +++ b/lib/Target/Alpha/AlphaJITInfo.cpp @@ -72,7 +72,7 @@ static void EmitBranchToAt(void *At, void *To) { void AlphaJITInfo::replaceMachineCodeForFunction(void *Old, void *New) { //FIXME - assert(0); + llvm_unreachable(); } static TargetJITInfo::JITCompilerFn JITCompilerFunction; @@ -241,7 +241,7 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR, long idx = 0; bool doCommon = true; switch ((Alpha::RelocationType)MR->getRelocationType()) { - default: assert(0 && "Unknown relocation type!"); + default: LLVM_UNREACHABLE("Unknown relocation type!"); case Alpha::reloc_literal: //This is a LDQl idx = MR->getGOTIndex(); @@ -281,7 +281,7 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR, DOUT << "LDA: " << idx << "\n"; break; default: - assert(0 && "Cannot handle gpdist yet"); + LLVM_UNREACHABLE("Cannot handle gpdist yet"); } break; case Alpha::reloc_bsr: { diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 1194a0fe3b..f1e651c6a8 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -307,7 +307,7 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF, } unsigned |