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-rw-r--r--lib/Target/Alpha/AlphaAsmPrinter.cpp1
-rw-r--r--lib/Target/Alpha/AlphaCodeEmitter.cpp5
-rw-r--r--lib/Target/Alpha/AlphaISelDAGToDAG.cpp1
-rw-r--r--lib/Target/Alpha/AlphaISelLowering.cpp5
-rw-r--r--lib/Target/CBackend/CBackend.cpp4
-rw-r--r--lib/Target/CBackend/Writer.cpp4
-rw-r--r--lib/Target/IA64/IA64ISelDAGToDAG.cpp8
-rw-r--r--lib/Target/PowerPC/PPCAsmPrinter.cpp2
-rw-r--r--lib/Target/PowerPC/PPCCodeEmitter.cpp1
-rw-r--r--lib/Target/PowerPC/PPCISelDAGToDAG.cpp2
-rw-r--r--lib/Target/PowerPC/PPCISelLowering.cpp2
-rw-r--r--lib/Target/PowerPC/PPCMachOWriter.cpp2
-rw-r--r--lib/Target/PowerPC/PPCRegisterInfo.cpp1
-rw-r--r--lib/Target/Sparc/SparcAsmPrinter.cpp2
-rw-r--r--lib/Target/X86/X86FloatingPoint.cpp1
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp10
-rwxr-xr-xlib/Target/X86/X86IntelAsmPrinter.cpp1
17 files changed, 11 insertions, 41 deletions
diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp
index f94f5537bc..821d432456 100644
--- a/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -97,7 +97,6 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
const MRegisterInfo &RI = *TM.getRegisterInfo();
- int new_symbol;
switch (MO.getType()) {
case MachineOperand::MO_Register:
diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp
index 82f31da007..15de348ee4 100644
--- a/lib/Target/Alpha/AlphaCodeEmitter.cpp
+++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp
@@ -92,7 +92,6 @@ void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
I != E; ++I) {
MachineInstr &MI = *I;
- unsigned Opcode = MI.getOpcode();
switch(MI.getOpcode()) {
default:
MCE.emitWordLE(getBinaryCodeForInstr(*I));
@@ -160,10 +159,6 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
} else if (MO.isGlobalAddress() || MO.isExternalSymbol()
|| MO.isConstantPoolIndex()) {
DEBUG(std::cerr << MO << " is a relocated op for " << MI << "\n";);
- bool isExternal = MO.isExternalSymbol() ||
- (MO.isGlobalAddress() &&
- ( MO.getGlobal()->hasWeakLinkage() ||
- MO.getGlobal()->isExternal()) );
unsigned Reloc = 0;
int Offset = 0;
bool useGOT = false;
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 8f09b2ef86..521e661dc0 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -324,7 +324,6 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
// val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
break; //(zext (LDAH (LDA)))
//Else use the constant pool
- MachineConstantPool *CP = BB->getParent()->getConstantPool();
ConstantInt *C = ConstantInt::get(Type::ULongTy, uval);
SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 0b8961ed14..9728d88a38 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -175,8 +175,6 @@ static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
SDOperand Zero = DAG.getConstant(0, PtrVT);
- const TargetMachine &TM = DAG.getTarget();
-
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
@@ -207,7 +205,6 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
int &VarArgsOffset) {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
- SSARegMap *RegMap = MF.getSSARegMap();
std::vector<SDOperand> ArgValues;
SDOperand Root = Op.getOperand(0);
@@ -225,7 +222,6 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
SDOperand ArgVal;
if (ArgNo < 6) {
- unsigned Vreg;
switch (ObjectVT) {
default:
std::cerr << "Unknown Type " << ObjectVT << "\n";
@@ -480,7 +476,6 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
//Expand only on constant case
if (Op.getOperand(1).getOpcode() == ISD::Constant) {
MVT::ValueType VT = Op.Val->getValueType(0);
- unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
BuildUDIV(Op.Val, DAG, NULL) :
BuildSDIV(Op.Val, DAG, NULL);
diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp
index 4a04e023ea..15bf06a6e2 100644
--- a/lib/Target/CBackend/CBackend.cpp
+++ b/lib/Target/CBackend/CBackend.cpp
@@ -702,7 +702,7 @@ void CWriter::printConstant(Constant *CPV) {
// The prefix for a quiet NaN is 0x7FF8. For a signalling NaN,
// it's 0x7ff4.
const unsigned long QuietNaN = 0x7ff8UL;
- const unsigned long SignalNaN = 0x7ff4UL;
+ //const unsigned long SignalNaN = 0x7ff4UL;
// We need to grab the first part of the FP #
char Buffer[100];
@@ -2140,7 +2140,7 @@ void CWriter::printIndexingExpression(Value *Ptr, gep_type_iterator I,
gep_type_iterator E) {
bool HasImplicitAddress = false;
// If accessing a global value with no indexing, avoid *(&GV) syndrome
- if (GlobalValue *V = dyn_cast<GlobalValue>(Ptr)) {
+ if (isa<GlobalValue>(Ptr)) {
HasImplicitAddress = true;
} else if (isDirectAlloca(Ptr)) {
HasImplicitAddress = true;
diff --git a/lib/Target/CBackend/Writer.cpp b/lib/Target/CBackend/Writer.cpp
index 4a04e023ea..15bf06a6e2 100644
--- a/lib/Target/CBackend/Writer.cpp
+++ b/lib/Target/CBackend/Writer.cpp
@@ -702,7 +702,7 @@ void CWriter::printConstant(Constant *CPV) {
// The prefix for a quiet NaN is 0x7FF8. For a signalling NaN,
// it's 0x7ff4.
const unsigned long QuietNaN = 0x7ff8UL;
- const unsigned long SignalNaN = 0x7ff4UL;
+ //const unsigned long SignalNaN = 0x7ff4UL;
// We need to grab the first part of the FP #
char Buffer[100];
@@ -2140,7 +2140,7 @@ void CWriter::printIndexingExpression(Value *Ptr, gep_type_iterator I,
gep_type_iterator E) {
bool HasImplicitAddress = false;
// If accessing a global value with no indexing, avoid *(&GV) syndrome
- if (GlobalValue *V = dyn_cast<GlobalValue>(Ptr)) {
+ if (isa<GlobalValue>(Ptr)) {
HasImplicitAddress = true;
} else if (isDirectAlloca(Ptr)) {
HasImplicitAddress = true;
diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index a79cf2ce32..fe60ee7e5d 100644
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -337,11 +337,9 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
CallOpcode = IA64::BRCALL_IPREL_GA;
CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
- } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
- // case for correctness, to avoid
- // "non-pic code with imm reloc.n
- // against dynamic symbol" errors
- dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
+ } else if (isa<ExternalSymbolSDNode>(N->getOperand(1))) {
+ // FIXME: we currently NEED this case for correctness, to avoid
+ // "non-pic code with imm reloc.n against dynamic symbol" errors
CallOpcode = IA64::BRCALL_IPREL_ES;
CallOperand = N->getOperand(1);
} else {
diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index aafc7825f4..ee57cbaaba 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -249,7 +249,6 @@ namespace {
DarwinAsmPrinter(std::ostream &O, PPCTargetMachine &TM,
const TargetAsmInfo *T)
: PPCAsmPrinter(O, TM, T), DW(O, this, T) {
- bool isPPC64 = Subtarget.isPPC64();
}
virtual const char *getPassName() const {
@@ -308,7 +307,6 @@ void PPCAsmPrinter::printOp(const MachineOperand &MO) {
// Computing the address of a global symbol, not calling it.
GlobalValue *GV = MO.getGlobal();
std::string Name = Mang->getValueName(GV);
- int offset = MO.getOffset();
// External or weakly linked global variables need non-lazily-resolved stubs
if (TM.getRelocationModel() != Reloc::Static) {
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index 464044aa52..c321cbcdee 100644
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -91,7 +91,6 @@ void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
MachineInstr &MI = *I;
- unsigned Opcode = MI.getOpcode();
switch (MI.getOpcode()) {
default:
MCE.emitWordBE(getBinaryCodeForInstr(*I));
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 2bfaa2d72e..aee156c444 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -1134,7 +1134,6 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
unsigned BROpc = getBCCForSetCC(CC);
- bool isFP = MVT::isFloatingPoint(N->getValueType(0));
unsigned SelectCCOp;
if (N->getValueType(0) == MVT::i32)
SelectCCOp = PPC::SELECT_CC_I4;
@@ -1218,7 +1217,6 @@ SDNode *PPCDAGToDAGISel::MySelect_PPCcall(SDOperand N) {
SDOperand Chain(0, 0);
SDOperand N1(0, 0);
SDOperand Tmp0(0, 0);
- SDNode *ResNode;
Chain = N.getOperand(0);
N1 = N.getOperand(1);
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 26a1f21275..184b4bfffb 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -942,9 +942,7 @@ static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
SDOperand Chain = Op.getOperand(0);
- unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
- bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
SDOperand Callee = Op.getOperand(4);
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
diff --git a/lib/Target/PowerPC/PPCMachOWriter.cpp b/lib/Target/PowerPC/PPCMachOWriter.cpp
index 8d6de73372..59068e1cbb 100644
--- a/lib/Target/PowerPC/PPCMachOWriter.cpp
+++ b/lib/Target/PowerPC/PPCMachOWriter.cpp
@@ -99,7 +99,7 @@ void PPCMachOWriter::GetTargetRelocation(MachineRelocation &MR,
case PPC::reloc_pcrel_bx:
Addr -= MR.getMachineCodeOffset();
Addr >>= 2;
- Addr & 0xFFFFFF;
+ // ??? Addr & 0xFFFFFF; Possibly this was supposed to be Addr &= 0xFFFFFF ?
Addr <<= 2;
Addr |= (MOS.SectionData[MR.getMachineCodeOffset()] << 24);
fixword(MOS.SectionData, Addr, MR.getMachineCodeOffset());
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 34c23bd1fa..98ada71eb0 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -370,7 +370,6 @@ MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
//
static bool hasFP(const MachineFunction &MF) {
const MachineFrameInfo *MFI = MF.getFrameInfo();
- unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
// If frame pointers are forced, or if there are variable sized stack objects,
// use a frame pointer.
diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp
index 1c251e1bea..2e6a470af8 100644
--- a/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -185,8 +185,6 @@ void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
return;
}
- MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
-
if (MI->getOperand(opNum+1).isRegister() &&
MI->getOperand(opNum+1).getReg() == SP::G0)
return; // don't print "+%g0"
diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index 832e09a53c..5a10d97103 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -106,7 +106,6 @@ namespace {
bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
if (!isAtTop(RegNo)) {
- unsigned Slot = getSlot(RegNo);
unsigned STReg = getSTReg(RegNo);
unsigned RegOnTop = getStackEntry(0);
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 92bec9174e..ac7327f9e9 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -532,7 +532,6 @@ SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG) {
SDOperand Chain = Op.getOperand(0);
unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
- bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
SDOperand Callee = Op.getOperand(4);
MVT::ValueType RetVT= Op.Val->getValueType(0);
@@ -1031,7 +1030,6 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
SDOperand
X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG) {
SDOperand Chain = Op.getOperand(0);
- unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
SDOperand Callee = Op.getOperand(4);
@@ -1528,8 +1526,6 @@ X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
bool isFastCall) {
SDOperand Chain = Op.getOperand(0);
- unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
- bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
SDOperand Callee = Op.getOperand(4);
MVT::ValueType RetVT= Op.Val->getValueType(0);
@@ -1549,11 +1545,13 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
{ X86::AX, X86::DX },
{ X86::EAX, X86::EDX }
};
+#if 0
static const unsigned FastCallGPRArgRegs[][2] = {
{ X86::CL, X86::DL },
{ X86::CX, X86::DX },
{ X86::ECX, X86::EDX }
};
+#endif
static const unsigned XMMArgRegs[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
};
@@ -1906,7 +1904,6 @@ SDOperand X86TargetLowering::LowerStdCallCCArguments(SDOperand Op,
SDOperand X86TargetLowering::LowerStdCallCCCallTo(SDOperand Op,
SelectionDAG &DAG) {
SDOperand Chain = Op.getOperand(0);
- unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
SDOperand Callee = Op.getOperand(4);
@@ -2841,7 +2838,7 @@ static bool isSplatMask(SDNode *N) {
unsigned i = 0;
for (; i != NumElems; ++i) {
SDOperand Elt = N->getOperand(i);
- if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) {
+ if (isa<ConstantSDNode>(Elt)) {
ElementBase = Elt;
break;
}
@@ -5431,7 +5428,6 @@ static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
- TargetMachine &TM = getTargetMachine();
SelectionDAG &DAG = DCI.DAG;
switch (N->getOpcode()) {
default: break;
diff --git a/lib/Target/X86/X86IntelAsmPrinter.cpp b/lib/Target/X86/X86IntelAsmPrinter.cpp
index 7b2396345c..91e1478211 100755
--- a/lib/Target/X86/X86IntelAsmPrinter.cpp
+++ b/lib/Target/X86/X86IntelAsmPrinter.cpp
@@ -386,7 +386,6 @@ bool X86IntelAsmPrinter::doFinalization(Module &M) {
std::string name = Mang->getValueName(I);
Constant *C = I->getInitializer();
- unsigned Size = TD->getTypeSize(C->getType());
unsigned Align = TD->getPreferredAlignmentLog(I);
bool bCustomSegment = false;
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-05 08:21:08 +0000