diff options
Diffstat (limited to 'lib/Target')
42 files changed, 173 insertions, 166 deletions
diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 92f2f5bf40..3758b0ddf0 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -64,8 +64,8 @@ extern "C" void LLVMInitializeARMTarget() { /// ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + Reloc::Model RM, CodeModel::Model CM) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS), JITInfo(), InstrItins(Subtarget.getInstrItineraryData()) { @@ -76,8 +76,8 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT, ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM) - : ARMBaseTargetMachine(T, TT, CPU, FS, RM), InstrInfo(Subtarget), + Reloc::Model RM, CodeModel::Model CM) + : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), InstrInfo(Subtarget), DataLayout(Subtarget.isAPCS_ABI() ? std::string("e-p:32:32-f64:32:64-i64:32:64-" "v128:32:128-v64:32:64-n32") : @@ -94,8 +94,8 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM) - : ARMBaseTargetMachine(T, TT, CPU, FS, RM), + Reloc::Model RM, CodeModel::Model CM) + : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), InstrInfo(Subtarget.hasThumb2() ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h index 616ea9c3d2..c8c601c301 100644 --- a/lib/Target/ARM/ARMTargetMachine.h +++ b/lib/Target/ARM/ARMTargetMachine.h @@ -40,7 +40,8 @@ private: public: ARMBaseTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual ARMJITInfo *getJITInfo() { return &JITInfo; } virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; } @@ -69,7 +70,8 @@ class ARMTargetMachine : public ARMBaseTargetMachine { ARMFrameLowering FrameLowering; public: ARMTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual const ARMRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); @@ -108,7 +110,8 @@ class ThumbTargetMachine : public ARMBaseTargetMachine { OwningPtr<ARMFrameLowering> FrameLowering; public: ThumbTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo virtual const ARMBaseRegisterInfo *getRegisterInfo() const { diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index 09bcf0231e..e64902ccfd 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -143,11 +143,12 @@ extern "C" void LLVMInitializeARMMCAsmInfo() { RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo); } -MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); if (RM == Reloc::Default) RM = Reloc::DynamicNoPIC; - X->InitMCCodeGenInfo(RM); + X->InitMCCodeGenInfo(RM, CM); return X; } diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp index 4cdd3ab483..df7194a561 100644 --- a/lib/Target/Alpha/AlphaTargetMachine.cpp +++ b/lib/Target/Alpha/AlphaTargetMachine.cpp @@ -23,9 +23,9 @@ extern "C" void LLVMInitializeAlphaTarget() { } AlphaTargetMachine::AlphaTargetMachine(const Target &T, StringRef TT, - StringRef CPU, - StringRef FS, Reloc::Model RM) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), DataLayout("e-f128:128:128-n64"), FrameLowering(Subtarget), Subtarget(TT, CPU, FS), diff --git a/lib/Target/Alpha/AlphaTargetMachine.h b/lib/Target/Alpha/AlphaTargetMachine.h index 1d930d0a5c..48bb948a79 100644 --- a/lib/Target/Alpha/AlphaTargetMachine.h +++ b/lib/Target/Alpha/AlphaTargetMachine.h @@ -37,7 +37,8 @@ class AlphaTargetMachine : public LLVMTargetMachine { public: AlphaTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameLowering *getFrameLowering() const { diff --git a/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp b/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp index 04bc434862..517ab18283 100644 --- a/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp +++ b/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp @@ -66,9 +66,10 @@ extern "C" void LLVMInitializeAlphaMCAsmInfo() { RegisterMCAsmInfo<AlphaMCAsmInfo> X(TheAlphaTarget); } -MCCodeGenInfo *createAlphaMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createAlphaMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); - X->InitMCCodeGenInfo(Reloc::PIC_); + X->InitMCCodeGenInfo(Reloc::PIC_, CM); return X; } diff --git a/lib/Target/Blackfin/BlackfinTargetMachine.cpp b/lib/Target/Blackfin/BlackfinTargetMachine.cpp index 0a474cdb68..add1c17ccb 100644 --- a/lib/Target/Blackfin/BlackfinTargetMachine.cpp +++ b/lib/Target/Blackfin/BlackfinTargetMachine.cpp @@ -24,8 +24,10 @@ extern "C" void LLVMInitializeBlackfinTarget() { BlackfinTargetMachine::BlackfinTargetMachine(const Target &T, StringRef TT, StringRef CPU, - StringRef FS, Reloc::Model RM) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + StringRef FS, + Reloc::Model RM, + CodeModel::Model CM) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), DataLayout("e-p:32:32-i64:32-f64:32-n32"), Subtarget(TT, CPU, FS), TLInfo(*this), diff --git a/lib/Target/Blackfin/BlackfinTargetMachine.h b/lib/Target/Blackfin/BlackfinTargetMachine.h index afe3919257..c85337fe23 100644 --- a/lib/Target/Blackfin/BlackfinTargetMachine.h +++ b/lib/Target/Blackfin/BlackfinTargetMachine.h @@ -36,7 +36,8 @@ namespace llvm { BlackfinIntrinsicInfo IntrinsicInfo; public: BlackfinTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual const BlackfinInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameLowering *getFrameLowering() const { diff --git a/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp b/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp index b4e89c1bbd..5b69a0f1ba 100644 --- a/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp +++ b/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp @@ -69,9 +69,10 @@ extern "C" void LLVMInitializeBlackfinMCAsmInfo() { RegisterMCAsmInfo<BlackfinMCAsmInfo> X(TheBlackfinTarget); } -MCCodeGenInfo *createBlackfinMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createBlackfinMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); - X->InitMCCodeGenInfo(RM); + X->InitMCCodeGenInfo(RM, CM); return X; } diff --git a/lib/Target/CBackend/CTargetMachine.h b/lib/Target/CBackend/CTargetMachine.h index e0af30de9a..4f1ca974de 100644 --- a/lib/Target/CBackend/CTargetMachine.h +++ b/lib/Target/CBackend/CTargetMachine.h @@ -21,7 +21,8 @@ namespace llvm { struct CTargetMachine : public TargetMachine { CTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM) + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM) : TargetMachine(T, TT, CPU, FS) {} virtual bool addPassesToEmitFile(PassManagerBase &PM, diff --git a/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp b/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp index a951f28219..1e09276d9e 100644 --- a/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp +++ b/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp @@ -78,11 +78,12 @@ extern "C" void LLVMInitializeCellSPUMCAsmInfo() { RegisterMCAsmInfoFn X(TheCellSPUTarget, createSPUMCAsmInfo); } -MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); // For the time being, use static relocations, since there's really no // support for PIC yet. - X->InitMCCodeGenInfo(Reloc::Static); + X->InitMCCodeGenInfo(Reloc::Static, CM); return X; } diff --git a/lib/Target/CellSPU/SPUTargetMachine.cpp b/lib/Target/CellSPU/SPUTargetMachine.cpp index 8eabe9209d..ea59a80e87 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.cpp +++ b/lib/Target/CellSPU/SPUTargetMachine.cpp @@ -32,8 +32,9 @@ SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const { } SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT, - StringRef CPU,StringRef FS, Reloc::Model RM) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), diff --git a/lib/Target/CellSPU/SPUTargetMachine.h b/lib/Target/CellSPU/SPUTargetMachine.h index b48a517f82..fffe77cabb 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.h +++ b/lib/Target/CellSPU/SPUTargetMachine.h @@ -39,7 +39,8 @@ class SPUTargetMachine : public LLVMTargetMachine { InstrItineraryData InstrItins; public: SPUTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); /// Return the subtarget implementation object virtual const SPUSubtarget *getSubtargetImpl() const { diff --git a/lib/Target/CppBackend/CPPTargetMachine.h b/lib/Target/CppBackend/CPPTargetMachine.h index 56f479502d..287e537271 100644 --- a/lib/Target/CppBackend/CPPTargetMachine.h +++ b/lib/Target/CppBackend/CPPTargetMachine.h @@ -23,7 +23,8 @@ class formatted_raw_ostream; struct CPPTargetMachine : public TargetMachine { CPPTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM) + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM) : TargetMachine(T, TT, CPU, FS) {} virtual bool addPassesToEmitFile(PassManagerBase &PM, diff --git a/lib/Target/MBlaze/MBlazeTargetMachine.cpp b/lib/Target/MBlaze/MBlazeTargetMachine.cpp index 945c847ae9..0f609d0fde 100644 --- a/lib/Target/MBlaze/MBlazeTargetMachine.cpp +++ b/lib/Target/MBlaze/MBlazeTargetMachine.cpp @@ -68,16 +68,15 @@ extern "C" void LLVMInitializeMBlazeTarget() { // an easier handling. MBlazeTargetMachine:: MBlazeTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM): - LLVMTargetMachine(T, TT, CPU, FS, RM), + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM): + LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS), DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"), InstrInfo(*this), FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this), ELFWriterInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { - if (getCodeModel() == CodeModel::Default) - setCodeModel(CodeModel::Small); } // Install an instruction selector pass using diff --git a/lib/Target/MBlaze/MBlazeTargetMachine.h b/lib/Target/MBlaze/MBlazeTargetMachine.h index 6f32d1439a..c1bc08aeb5 100644 --- a/lib/Target/MBlaze/MBlazeTargetMachine.h +++ b/lib/Target/MBlaze/MBlazeTargetMachine.h @@ -42,7 +42,8 @@ namespace llvm { public: MBlazeTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual const MBlazeInstrInfo *getInstrInfo() const { return &InstrInfo; } diff --git a/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp b/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp index 22ce1cb8b6..aa4399b839 100644 --- a/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp +++ b/lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp @@ -75,11 +75,14 @@ extern "C" void LLVMInitializeMBlazeMCAsmInfo() { RegisterMCAsmInfoFn X(TheMBlazeTarget, createMCAsmInfo); } -MCCodeGenInfo *createMBlazeMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createMBlazeMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); if (RM == Reloc::Default) - RM = Reloc::Static; - X->InitMCCodeGenInfo(RM); + RM = Reloc::Static; + if (CM == CodeModel::Default) + CM = CodeModel::Small; + X->InitMCCodeGenInfo(RM, CM); return X; } diff --git a/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp b/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp index 6aa62206ef..60b80c3607 100644 --- a/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp +++ b/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp @@ -67,9 +67,10 @@ extern "C" void LLVMInitializeMSP430MCAsmInfo() { RegisterMCAsmInfo<MSP430MCAsmInfo> X(TheMSP430Target); } -MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); - X->InitMCCodeGenInfo(RM); + X->InitMCCodeGenInfo(RM, CM); return X; } diff --git a/lib/Target/MSP430/MSP430TargetMachine.cpp b/lib/Target/MSP430/MSP430TargetMachine.cpp index 85ca533005..12a624abd1 100644 --- a/lib/Target/MSP430/MSP430TargetMachine.cpp +++ b/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -27,8 +27,9 @@ extern "C" void LLVMInitializeMSP430Target() { MSP430TargetMachine::MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, - StringRef FS, Reloc::Model RM) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + StringRef FS, + Reloc::Model RM, CodeModel::Model CM) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS), // FIXME: Check TargetData string. DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"), diff --git a/lib/Target/MSP430/MSP430TargetMachine.h b/lib/Target/MSP430/MSP430TargetMachine.h index 384176c1ed..eb483dc870 100644 --- a/lib/Target/MSP430/MSP430TargetMachine.h +++ b/lib/Target/MSP430/MSP430TargetMachine.h @@ -39,7 +39,8 @@ class MSP430TargetMachine : public LLVMTargetMachine { public: MSP430TargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); virtual const TargetFrameLowering *getFrameLowering() const { return &FrameLowering; diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp index b83a69d06a..a4d6dcfc88 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -78,7 +78,8 @@ extern "C" void LLVMInitializeMipsMCAsmInfo() { RegisterMCAsmInfoFn Y(TheMipselTarget, createMipsMCAsmInfo); } -MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); if (RM == Reloc::Default) { // Abicall enables PIC by default @@ -88,7 +89,7 @@ MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM) { else RM = Reloc::PIC_; } - X->InitMCCodeGenInfo(RM); + X->InitMCCodeGenInfo(RM, CM); return X; } diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index a195a48961..703d9e7002 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -32,9 +32,10 @@ extern "C" void LLVMInitializeMipsTarget() { // Using CodeModel::Large enables different CALL behavior. MipsTargetMachine:: MipsTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM, + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM, bool isLittle=false): - LLVMTargetMachine(T, TT, CPU, FS, RM), + LLVMTargetMachine(T, TT, CPU, FS, RM, CM), Subtarget(TT, CPU, FS, isLittle), DataLayout(isLittle ? std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") : @@ -46,8 +47,9 @@ MipsTargetMachine(const Target &T, StringRef TT, MipselTargetMachine:: MipselTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM) : - MipsTargetMachine(T, TT, CPU, FS, RM, true) {} + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM) : + MipsTargetMachine(T, TT, CPU, FS, RM, CM, true) {} // Install an instruction selector pass using // the ISelDag to gen Mips code. diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h index c1671e69bb..421405649a 100644 --- a/lib/Target/Mips/MipsTargetMachine.h +++ b/lib/Target/Mips/MipsTargetMachine.h @@ -36,7 +36,8 @@ namespace llvm { public: MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, bool isLittle); + Reloc::Model RM, CodeModel::Model CM, + bool isLittle); virtual const MipsInstrInfo *getInstrInfo() const { return &InstrInfo; } @@ -74,7 +75,8 @@ namespace llvm { class MipselTargetMachine : public MipsTargetMachine { public: MipselTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, Reloc::Model RM); + StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM); }; } // End llvm namespace diff --git a/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp b/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp index 19d0c6dfa4..84f472f74e 100644 --- a/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp +++ b/lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp @@ -71,9 +71,10 @@ extern "C" void LLVMInitializePTXMCAsmInfo() { RegisterMCAsmInfo<PTXMCAsmInfo> Y(ThePTX64Target); } -MCCodeGenInfo *createPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM) { +MCCodeGenInfo *createPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM, + CodeModel::Model CM) { MCCodeGenInfo *X = new MCCodeGenInfo(); - X->InitMCCodeGenInfo(RM); + X->InitMCCodeGenInfo(RM, CM); return X; } diff --git a/lib/Target/PTX/PTXTargetMachine.cpp b/lib/Target/PTX/PTXTargetMachine.cpp index 2d73599e8d..ff9776a7f1 100644 --- a/lib/Target/PTX/PTXTargetMachine.cpp +++ b/lib/Target/PTX/PTXTargetMachine.cpp @@ -47,11 +47,10 @@ namespace { // DataLayout and FrameLowering are filled with dummy data PTXTargetMachine::PTXTargetMachine(const Target &T, - StringRef TT, - StringRef CPU, - StringRef FS, - Reloc::Model RM, bool is64Bit) - : LLVMTargetMachine(T, TT, CPU, FS, RM), + StringRef TT, StringRef CPU, StringRef FS, + Reloc::Model RM, CodeModel::Model CM, + bool is64Bit) + : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), DataLayout(is64Bit ? DataLayout64 : DataLayout32), Subtarget(TT, CPU, FS, is64Bit), FrameLowering(Subtarget), @@ -61,14 +60,14 @@ PTXTargetMachine::PTXTargetMachine(const Target &T, PTX32TargetMachine::PTX32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM) - : PTXTargetMachine(T, TT, CPU, FS, RM, false) { + Reloc::Model RM, CodeModel::Model CM) + : PTXTargetMachine(T, TT, CPU, FS, RM, CM, false) { } PTX64TargetMachine::PTX64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM) - : PTXTargetMachine(T, TT, CPU, FS, RM, true) { + Reloc::Model RM, CodeModel::Model CM) + : PTXTargetMachine(T, TT, CPU, FS, RM, CM, true) { } bool PTXTargetMachine::addInstSelector(PassManagerBase &PM, diff --git a/lib/Target/PTX/PTXTargetMachine.h b/lib/Target/PTX/PTXTargetMachine.h index 880e8d4add..3cf081fc4e 100644 --- a/lib/Target/PTX/PTXTargetMachin |