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-rw-r--r--lib/Target/Target.td14
1 files changed, 11 insertions, 3 deletions
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index b4584244d0..407ad64059 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -171,7 +171,7 @@ class Instruction {
bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
bit noResults = 0; // Does this instruction produce no results?
- InstrItinClass Itinerary; // Execution steps used for scheduling.
+ InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
}
/// Predicates - These are extra conditionals which are turned into instruction
@@ -213,8 +213,6 @@ def i64imm : Operand<i64>;
// which are global to the the target machine.
//
class InstrInfo {
- Instruction PHIInst;
-
// If the target wants to associate some target-specific information with each
// instruction, it should provide these two lists to indicate how to assemble
// the target specific information into the 32 bits available.
@@ -229,6 +227,16 @@ class InstrInfo {
bit isLittleEndianEncoding = 0;
}
+// Standard Instructions.
+def PHI : Instruction {
+ let OperandList = (ops variable_ops);
+ let AsmString = "PHINODE";
+}
+def INLINEASM : Instruction {
+ let OperandList = (ops variable_ops);
+ let AsmString = "";
+}
+
//===----------------------------------------------------------------------===//
// AsmWriter - This class can be implemented by targets that need to customize
// the format of the .s file writer.