aboutsummaryrefslogtreecommitdiff
path: root/lib/Target/SparcV9/RegAlloc
diff options
context:
space:
mode:
Diffstat (limited to 'lib/Target/SparcV9/RegAlloc')
-rw-r--r--lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp8
-rw-r--r--lib/Target/SparcV9/RegAlloc/LiveRange.h2
-rw-r--r--lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp100
-rw-r--r--lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h4
-rw-r--r--lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp120
-rw-r--r--lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h8
-rw-r--r--lib/Target/SparcV9/RegAlloc/RegClass.cpp16
-rw-r--r--lib/Target/SparcV9/RegAlloc/RegClass.h10
8 files changed, 134 insertions, 134 deletions
diff --git a/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp b/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp
index 19ffce1f71..eea17d7428 100644
--- a/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp
+++ b/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp
@@ -68,7 +68,7 @@ void InterferenceGraph::createGraph()
// init IG matrix
for(unsigned int i=0; i < Size; i++)
for(unsigned int j=0; j < Size; j++)
- IG[i][j] = 0;
+ IG[i][j] = 0;
}
//-----------------------------------------------------------------------------
@@ -88,7 +88,7 @@ void InterferenceGraph::addLRToIG(V9LiveRange *const LR)
// that there is some wrong logic in some other method.
//-----------------------------------------------------------------------------
void InterferenceGraph::setInterference(const V9LiveRange *const LR1,
- const V9LiveRange *const LR2 ) {
+ const V9LiveRange *const LR2 ) {
assert(LR1 != LR2);
IGNode *IGNode1 = LR1->getUserIGNode();
@@ -147,7 +147,7 @@ unsigned InterferenceGraph::getInterference(const V9LiveRange *const LR1,
//----------------------------------------------------------------------------
void InterferenceGraph::mergeIGNodesOfLRs(const V9LiveRange *LR1,
- V9LiveRange *LR2) {
+ V9LiveRange *LR2) {
assert( LR1 != LR2); // cannot merge the same live range
@@ -226,7 +226,7 @@ void InterferenceGraph::printIG() const {
std::cerr << " [" << i << "] ";
for( unsigned int j=0; j < Size; j++)
- if(IG[i][j])
+ if(IG[i][j])
std::cerr << "(" << i << "," << j << ") ";
std::cerr << "\n";
}
diff --git a/lib/Target/SparcV9/RegAlloc/LiveRange.h b/lib/Target/SparcV9/RegAlloc/LiveRange.h
index 31a9d0db2c..0eecb87da7 100644
--- a/lib/Target/SparcV9/RegAlloc/LiveRange.h
+++ b/lib/Target/SparcV9/RegAlloc/LiveRange.h
@@ -184,7 +184,7 @@ public:
}
};
-static inline std::ostream &operator << (std::ostream &os,
+static inline std::ostream &operator << (std::ostream &os,
const V9LiveRange &lr) {
os << "LiveRange@" << (void *)(&lr);
return os;
diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
index 4bbf517aea..59dd83db36 100644
--- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
+++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
@@ -30,7 +30,7 @@ namespace llvm {
unsigned V9LiveRange::getRegClassID() const { return getRegClass()->getID(); }
LiveRangeInfo::LiveRangeInfo(const Function *F, const TargetMachine &tm,
- std::vector<RegClass *> &RCL)
+ std::vector<RegClass *> &RCL)
: Meth(F), TM(tm), RegClassList(RCL), MRI(*tm.getRegInfo()) { }
@@ -177,15 +177,15 @@ void LiveRangeInfo::constructLiveRanges() {
// CallRetInstrList for processing its args, ret value, and ret addr.
//
if(TM.getInstrInfo()->isReturn(MInst->getOpcode()) ||
- TM.getInstrInfo()->isCall(MInst->getOpcode()))
- CallRetInstrList.push_back(MInst);
+ TM.getInstrInfo()->isCall(MInst->getOpcode()))
+ CallRetInstrList.push_back(MInst);
// iterate over explicit MI operands and create a new LR
// for each operand that is defined by the instruction
for (MachineInstr::val_op_iterator OpI = MInst->begin(),
OpE = MInst->end(); OpI != OpE; ++OpI)
- if (OpI.isDef()) {
- const Value *Def = *OpI;
+ if (OpI.isDef()) {
+ const Value *Def = *OpI;
bool isCC = (OpI.getMachineOperand().getType()
== MachineOperand::MO_CCRegister);
V9LiveRange* LR = createOrAddToLiveRange(Def, isCC);
@@ -197,13 +197,13 @@ void LiveRangeInfo::constructLiveRanges() {
LR->setColor(MRI.getClassRegNum(OpI.getMachineOperand().getReg(),
getClassId));
}
- }
+ }
// iterate over implicit MI operands and create a new LR
// for each operand that is defined by the instruction
for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i)
- if (MInst->getImplicitOp(i).isDef()) {
- const Value *Def = MInst->getImplicitRef(i);
+ if (MInst->getImplicitOp(i).isDef()) {
+ const Value *Def = MInst->getImplicitRef(i);
V9LiveRange* LR = createOrAddToLiveRange(Def, /*isCC*/ false);
// If the implicit operand has a pre-assigned register,
@@ -214,7 +214,7 @@ void LiveRangeInfo::constructLiveRanges() {
MInst->getImplicitOp(i).getReg(),
getClassId));
}
- }
+ }
} // for all machine instructions in the BB
} // for all BBs in function
@@ -265,10 +265,10 @@ void LiveRangeInfo::suggestRegs4CallRets() {
for each definition (def) in inst
for each operand (op) of inst that is a use
if the def and op are of the same register type
- if the def and op do not interfere //i.e., not simultaneously live
- if (degree(LR of def) + degree(LR of op)) <= # avail regs
- if both LRs do not have suggested colors
- merge2IGNodes(def, op) // i.e., merge 2 LRs
+ if the def and op do not interfere //i.e., not simultaneously live
+ if (degree(LR of def) + degree(LR of op)) <= # avail regs
+ if both LRs do not have suggested colors
+ merge2IGNodes(def, op) // i.e., merge 2 LRs
*/
//---------------------------------------------------------------------------
@@ -332,40 +332,40 @@ void LiveRangeInfo::coalesceLRs()
const MachineInstr *MI = MII;
if( DEBUG_RA >= RA_DEBUG_LiveRanges) {
- std::cerr << " *Iterating over machine instr ";
- MI->dump();
- std::cerr << "\n";
+ std::cerr << " *Iterating over machine instr ";
+ MI->dump();
+ std::cerr << "\n";
}
// iterate over MI operands to find defs
for(MachineInstr::const_val_op_iterator DefI = MI->begin(),
DefE = MI->end(); DefI != DefE; ++DefI) {
- if (DefI.isDef()) { // this operand is modified
- V9LiveRange *LROfDef = getLiveRangeForValue( *DefI );
- RegClass *RCOfDef = LROfDef->getRegClass();
+ if (DefI.isDef()) { // this operand is modified
+ V9LiveRange *LROfDef = getLiveRangeForValue( *DefI );
+ RegClass *RCOfDef = LROfDef->getRegClass();
- MachineInstr::const_val_op_iterator UseI = MI->begin(),
+ MachineInstr::const_val_op_iterator UseI = MI->begin(),
UseE = MI->end();
- for( ; UseI != UseE; ++UseI) { // for all uses
- V9LiveRange *LROfUse = getLiveRangeForValue( *UseI );
- if (!LROfUse) { // if LR of use is not found
- //don't warn about labels
- if (!isa<BasicBlock>(*UseI) && DEBUG_RA >= RA_DEBUG_LiveRanges)
- std::cerr << " !! Warning: No LR for use " << RAV(*UseI)<< "\n";
- continue; // ignore and continue
- }
-
- if (LROfUse == LROfDef) // nothing to merge if they are same
- continue;
-
- if (MRI.getRegTypeForLR(LROfDef) ==
+ for( ; UseI != UseE; ++UseI) { // for all uses
+ V9LiveRange *LROfUse = getLiveRangeForValue( *UseI );
+ if (!LROfUse) { // if LR of use is not found
+ //don't warn about labels
+ if (!isa<BasicBlock>(*UseI) && DEBUG_RA >= RA_DEBUG_LiveRanges)
+ std::cerr << " !! Warning: No LR for use " << RAV(*UseI)<< "\n";
+ continue; // ignore and continue
+ }
+
+ if (LROfUse == LROfDef) // nothing to merge if they are same
+ continue;
+
+ if (MRI.getRegTypeForLR(LROfDef) ==
MRI.getRegTypeForLR(LROfUse)) {
- // If the two RegTypes are the same
- if (!RCOfDef->getInterference(LROfDef, LROfUse) ) {
+ // If the two RegTypes are the same
+ if (!RCOfDef->getInterference(LROfDef, LROfUse) ) {
- unsigned CombinedDegree =
- LROfDef->getUserIGNode()->getNumOfNeighbors() +
- LROfUse->getUserIGNode()->getNumOfNeighbors();
+ unsigned CombinedDegree =
+ LROfDef->getUserIGNode()->getNumOfNeighbors() +
+ LROfUse->getUserIGNode()->getNumOfNeighbors();
if (CombinedDegree > RCOfDef->getNumOfAvailRegs()) {
// get more precise estimate of combined degree
@@ -373,19 +373,19 @@ void LiveRangeInfo::coalesceLRs()
getCombinedDegree(LROfUse->getUserIGNode());
}
- if (CombinedDegree <= RCOfDef->getNumOfAvailRegs()) {
- // if both LRs do not have different pre-assigned colors
- // and both LRs do not have suggested colors
+ if (CombinedDegree <= RCOfDef->getNumOfAvailRegs()) {
+ // if both LRs do not have different pre-assigned colors
+ // and both LRs do not have suggested colors
if (! InterfsPreventCoalescing(*LROfDef, *LROfUse)) {
- RCOfDef->mergeIGNodesOfLRs(LROfDef, LROfUse);
- unionAndUpdateLRs(LROfDef, LROfUse);
- }
-
- } // if combined degree is less than # of regs
- } // if def and use do not interfere
- }// if reg classes are the same
- } // for all uses
- } // if def
+ RCOfDef->mergeIGNodesOfLRs(LROfDef, LROfUse);
+ unionAndUpdateLRs(LROfDef, LROfUse);
+ }
+
+ } // if combined degree is less than # of regs
+ } // if def and use do not interfere
+ }// if reg classes are the same
+ } // for all uses
+ } // if def
} // for all defs
} // for all machine instructions
} // for all BBs
diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h
index 5344d23382..0463f51760 100644
--- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h
+++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h
@@ -78,8 +78,8 @@ class LiveRangeInfo {
public:
LiveRangeInfo(const Function *F,
- const TargetMachine& tm,
- std::vector<RegClass *> & RCList);
+ const TargetMachine& tm,
+ std::vector<RegClass *> & RCList);
/// Destructor to destroy all LiveRanges in the V9LiveRange Map
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index cc2695c1ac..3bdcef4fc2 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -131,7 +131,7 @@ void PhyRegAlloc::createIGNodeListsAndIGs() {
/// instruction.
///
void PhyRegAlloc::addInterference(const Value *Def, const ValueSet *LVSet,
- bool isCallInst) {
+ bool isCallInst) {
ValueSet::const_iterator LIt = LVSet->begin();
// get the live range of instruction
@@ -167,7 +167,7 @@ void PhyRegAlloc::addInterference(const Value *Def, const ValueSet *LVSet,
/// the return value does not interfere with that call itself).
///
void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
- const ValueSet *LVSetAft) {
+ const ValueSet *LVSetAft) {
if (DEBUG_RA >= RA_DEBUG_Interference)
std::cerr << "\n For call inst: " << *MInst;
@@ -185,7 +185,7 @@ void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
std::cerr << "\n\tLR after Call: " << *LR << "\n";
LR->setCallInterference();
if (DEBUG_RA >= RA_DEBUG_Interference)
- std::cerr << "\n ++After adding call interference for LR: " << *LR << "\n";
+ std::cerr << "\n ++After adding call interference for LR: " << *LR << "\n";
}
}
@@ -242,29 +242,29 @@ void PhyRegAlloc::buildInterferenceGraphs() {
bool isCallInst = TM.getInstrInfo()->isCall(MInst->getOpcode());
if (isCallInst) {
- // set the isCallInterference flag of each live range which extends
- // across this call instruction. This information is used by graph
- // coloring algorithm to avoid allocating volatile colors to live ranges
- // that span across calls (since they have to be saved/restored)
- setCallInterferences(MInst, &LVSetAI);
+ // set the isCallInterference flag of each live range which extends
+ // across this call instruction. This information is used by graph
+ // coloring algorithm to avoid allocating volatile colors to live ranges
+ // that span across calls (since they have to be saved/restored)
+ setCallInterferences(MInst, &LVSetAI);
}
// iterate over all MI operands to find defs
for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
OpE = MInst->end(); OpI != OpE; ++OpI) {
- if (OpI.isDef()) // create a new LR since def
- addInterference(*OpI, &LVSetAI, isCallInst);
+ if (OpI.isDef()) // create a new LR since def
+ addInterference(*OpI, &LVSetAI, isCallInst);
- // Calculate the spill cost of each live range
- V9LiveRange *LR = LRI->getLiveRangeForValue(*OpI);
- if (LR) LR->addSpillCost(BBLoopDepthCost);
+ // Calculate the spill cost of each live range
+ V9LiveRange *LR = LRI->getLiveRangeForValue(*OpI);
+ if (LR) LR->addSpillCost(BBLoopDepthCost);
}
// Also add interference for any implicit definitions in a machine
// instr (currently, only calls have this).
unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
for (unsigned z=0; z < NumOfImpRefs; z++)
if (MInst->getImplicitOp(z).isDef())
- addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
+ addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
} // for all machine instructions in BB
} // for all BBs in function
@@ -294,13 +294,13 @@ void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
const V9LiveRange *LROfOp2 = LRI->getLiveRangeForValue(*It2);
if (LROfOp2) {
- RegClass *RCOfOp1 = LROfOp1->getRegClass();
- RegClass *RCOfOp2 = LROfOp2->getRegClass();
+ RegClass *RCOfOp1 = LROfOp1->getRegClass();
+ RegClass *RCOfOp2 = LROfOp2->getRegClass();
- if (RCOfOp1 == RCOfOp2 ){
- RCOfOp1->setInterference( LROfOp1, LROfOp2 );
- setInterf = true;
- }
+ if (RCOfOp1 == RCOfOp2 ){
+ RCOfOp1->setInterference( LROfOp1, LROfOp2 );
+ setInterf = true;
+ }
} // if Op2 has a LR
} // for all other defs in machine instr
} // for all operands in an instruction
@@ -556,7 +556,7 @@ void PhyRegAlloc::updateMachineCode()
// do not process Phis
if (MInst->getOpcode() == V9::PHI)
- continue;
+ continue;
// if there are any added instructions...
if (AddedInstrMap.count(MInst)) {
@@ -614,14 +614,14 @@ void PhyRegAlloc::updateMachineCode()
void PhyRegAlloc::insertCode4SpilledLR(const V9LiveRange *LR,
MachineBasicBlock::iterator& MII,
MachineBasicBlock &MBB,
- const unsigned OpNum) {
+ const unsigned OpNum) {
MachineInstr *MInst = MII;
const BasicBlock *BB = MBB.getBasicBlock();
assert((! TM.getInstrInfo()->isCall(MInst->getOpcode()) || OpNum == 0) &&
"Outgoing arg of a call must be handled elsewhere (func arg ok)");
assert(! TM.getInstrInfo()->isReturn(MInst->getOpcode()) &&
- "Return value of a ret must be handled elsewhere");
+ "Return value of a ret must be handled elsewhere");
MachineOperand& Op = MInst->getOperand(OpNum);
bool isDef = Op.isDef();
@@ -778,33 +778,33 @@ PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
if (LR) {
if (! LR->isMarkedForSpill()) {
assert(LR->hasColor() && "LR is neither spilled nor colored?");
- unsigned RCID = LR->getRegClassID();
- unsigned Color = LR->getColor();
-
- if (MRI.isRegVolatile(RCID, Color) ) {
- // if this is a call to the first-level reoptimizer
- // instrumentation entry point, and the register is not
- // modified by call, don't save and restore it.
- if (isLLVMFirstTrigger && !MRI.modifiedByCall(RCID, Color))
- continue;
-
- // if the value is in both LV sets (i.e., live before and after
- // the call machine instruction)
- unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
-
- // if we haven't already pushed this register...
- if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
- unsigned RegType = MRI.getRegTypeForLR(LR);
-
- // Now get two instructions - to push on stack and pop from stack
- // and add them to InstrnsBefore and InstrnsAfter of the
- // call instruction
- int StackOff =
+ unsigned RCID = LR->getRegClassID();
+ unsigned Color = LR->getColor();
+
+ if (MRI.isRegVolatile(RCID, Color) ) {
+ // if this is a call to the first-level reoptimizer
+ // instrumentation entry point, and the register is not
+ // modified by call, don't save and restore it.
+ if (isLLVMFirstTrigger && !MRI.modifiedByCall(RCID, Color))
+ continue;
+
+ // if the value is in both LV sets (i.e., live before and after
+ // the call machine instruction)
+ unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
+
+ // if we haven't already pushed this register...
+ if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
+ unsigned RegType = MRI.getRegTypeForLR(LR);
+
+ // Now get two instructions - to push on stack and pop from stack
+ // and add them to InstrnsBefore and InstrnsAfter of the
+ // call instruction
+ int StackOff =
MF->getInfo<SparcV9FunctionInfo>()->pushTempValue(MRI.getSpilledRegSize(RegType));
- //---- Insert code for pushing the reg on stack ----------
+ //---- Insert code for pushing the reg on stack ----------
- std::vector<MachineInstr*> AdIBef, AdIAft;
+ std::vector<MachineInstr*> AdIBef, AdIAft;
// We may need a scratch register to copy the saved value
// to/from memory. This may itself have to insert code to
@@ -834,8 +834,8 @@ PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
instrnsBefore.insert(instrnsBefore.end(),
AdIAft.begin(), AdIAft.end());
- //---- Insert code for popping the reg from the stack ----------
- AdIBef.clear();
+ //---- Insert code for popping the reg from the stack ----------
+ AdIBef.clear();
AdIAft.clear();
// We may need a scratch register to copy the saved value
@@ -855,26 +855,26 @@ PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
instrnsAfter.insert(instrnsAfter.end(),
AdIBef.begin(), AdIBef.end());
- MRI.cpMem2RegMI(instrnsAfter, MRI.getFramePointer(), StackOff,
+ MRI.cpMem2RegMI(instrnsAfter, MRI.getFramePointer(), StackOff,
Reg, RegType, scratchReg);
if (AdIAft.size() > 0)
instrnsAfter.insert(instrnsAfter.end(),
AdIAft.begin(), AdIAft.end());
-
- PushedRegSet.insert(Reg);
+
+ PushedRegSet.insert(Reg);
- if(DEBUG_RA) {
- std::cerr << "\nFor call inst:" << *CallMI;
- std::cerr << " -inserted caller saving instrs: Before:\n\t ";
+ if(DEBUG_RA) {
+ std::cerr << "\nFor call inst:" << *CallMI;
+ std::cerr << " -inserted caller saving instrs: Before:\n\t ";
for_each(instrnsBefore.begin(), instrnsBefore.end(),
std::mem_fun(&MachineInstr::dump));
- std::cerr << " -and After:\n\t ";
+ std::cerr << " -and After:\n\t ";
for_each(instrnsAfter.begin(), instrnsAfter.end(),
std::mem_fun(&MachineInstr::dump));
- }
- } // if not already pushed
- } // if LR has a volatile color
+ }
+ } // if not already pushed
+ } // if LR has a volatile color
} // if LR has color
} // if there is a LR for Var
} // for each value in the LV set after instruction
@@ -1280,7 +1280,7 @@ bool PhyRegAlloc::runOnFunction (Function &F) {
// RegClassList. This must be done before calling constructLiveRanges().
for (unsigned rc = 0; rc != NumOfRegClasses; ++rc)
RegClassList.push_back (new RegClass (Fn, TM.getRegInfo(),
- MRI.getMachineRegClass(rc)));
+ MRI.getMachineRegClass(rc)));
LRI->constructLiveRanges(); // create LR info
if (DEBUG_RA >= RA_DEBUG_LiveRanges)
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h
index c67d4781d2..78f4b47bf8 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h
@@ -118,7 +118,7 @@ private:
SavedStateMapTy FnAllocState;
void addInterference(const Value *Def, const ValueSet *LVSet,
- bool isCallInst);
+ bool isCallInst);
bool markAllocatedRegs(MachineInstr* MInst);
void addInterferencesForArgs();
@@ -131,10 +131,10 @@ private:
void finishSavingState(Module &M);
void setCallInterferences(const MachineInstr *MI,
- const ValueSet *LVSetAft);
+ const ValueSet *LVSetAft);
void move2DelayedInstr(const MachineInstr *OrigMI,
- const MachineInstr *DelayedMI);
+ const MachineInstr *DelayedMI);
void markUnusableSugColors();
void allocateStackSpace4SpilledLRs();
@@ -158,7 +158,7 @@ private:
MachineBasicBlock &MBB);
int getUsableUniRegAtMI(int RegType, const ValueSet *LVSetBef,
- MachineInstr *MI,
+ MachineInstr *MI,
std::vector<MachineInstr*>& MIBef,
std::vector<MachineInstr*>& MIAft);
diff --git a/lib/Target/SparcV9/RegAlloc/RegClass.cpp b/lib/Target/SparcV9/RegAlloc/RegClass.cpp
index fab53f1df4..dab86e02a1 100644
--- a/lib/Target/SparcV9/RegAlloc/RegClass.cpp
+++ b/lib/Target/SparcV9/RegAlloc/RegClass.cpp
@@ -25,7 +25,7 @@ namespace llvm {
//----------------------------------------------------------------------------
RegClass::RegClass(const Function *M,
const SparcV9RegInfo *_MRI_,
- const TargetRegClassInfo *_MRC_)
+ const TargetRegClassInfo *_MRC_)
: Meth(M), MRI(_MRI_), MRC(_MRC_),
RegClassID( _MRC_->getRegClassID() ),
IG(this), IGNodeStack() {
@@ -136,7 +136,7 @@ bool RegClass::pushUnconstrainedIGNodes()
IGNode->pushOnStack(); // set OnStack and dec deg of neighs
if (DEBUG_RA >= RA_DEBUG_Coloring) {
- std::cerr << " pushed un-constrained IGNode " << IGNode->getIndex()
+ std::cerr << " pushed un-constrained IGNode " << IGNode->getIndex()
<< " on to stack\n";
}
}
@@ -169,15 +169,15 @@ IGNode * RegClass::getIGNodeWithMinSpillCost() {
if (!IGNode->isOnStack()) {
double SpillCost = (double) IGNode->getParentLR()->getSpillCost() /
- (double) (IGNode->getCurDegree() + 1);
+ (double) (IGNode->getCurDegree() + 1);
if (isFirstNode) { // for the first IG node
- MinSpillCost = SpillCost;
- MinCostIGNode = IGNode;
- isFirstNode = false;
+ MinSpillCost = SpillCost;
+ MinCostIGNode = IGNode;
+ isFirstNode = false;
} else if (MinSpillCost > SpillCost) {
- MinSpillCost = SpillCost;
- MinCostIGNode = IGNode;
+ MinSpillCost = SpillCost;
+ MinCostIGNode = IGNode;
}
}
}
diff --git a/lib/Target/SparcV9/RegAlloc/RegClass.h b/lib/Target/SparcV9/RegAlloc/RegClass.h
index 1ed75a981e..667efe961d 100644
--- a/lib/Target/SparcV9/RegAlloc/RegClass.h
+++ b/lib/Target/SparcV9/RegAlloc/RegClass.h
@@ -87,8 +87,8 @@ class RegClass {
public:
RegClass(const Function *M,
- const SparcV9RegInfo *_MRI_,
- const TargetRegClassInfo *_MRC_);
+ const SparcV9RegInfo *_MRI_,
+ const TargetRegClassInfo *_MRC_);
inline void createInterferenceGraph() { IG.createGraph(); }
@@ -113,15 +113,15 @@ class RegClass {
{ IG.addLRToIG(LR); }
inline void setInterference(const V9LiveRange *const LR1,
- const V9LiveRange *const LR2)
+ const V9LiveRange *const LR2)
{ IG.setInterference(LR1, LR2); }
inline unsigned getInterference(const V9LiveRange *const LR1,
- const V9LiveRange *const LR2) const
+ const V9LiveRange *const LR2) const
{ return IG.getInterference(LR1, LR2); }
inline void mergeIGNodesOfLRs(const V9LiveRange *const LR1,
- V9LiveRange *const LR2)
+ V9LiveRange *const LR2)
{ IG.mergeIGNodesOfLRs(LR1, LR2); }
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-08-09 08:57:18 +0000