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-rw-r--r--lib/Target/Sparc/DelaySlotFiller.cpp4
-rw-r--r--lib/Target/Sparc/FPMover.cpp4
-rw-r--r--lib/Target/Sparc/Sparc.h4
-rw-r--r--lib/Target/Sparc/SparcAsmPrinter.cpp26
-rw-r--r--lib/Target/Sparc/SparcInstrInfo.cpp4
-rw-r--r--lib/Target/Sparc/SparcInstrInfo.h4
-rw-r--r--lib/Target/Sparc/SparcRegisterInfo.cpp10
-rw-r--r--lib/Target/Sparc/SparcRegisterInfo.h6
-rw-r--r--lib/Target/Sparc/SparcTargetMachine.cpp16
-rw-r--r--lib/Target/Sparc/SparcTargetMachine.h8
-rw-r--r--lib/Target/Sparc/SparcV8CodeEmitter.cpp8
-rw-r--r--lib/Target/Sparc/SparcV8ISelSimple.cpp64
-rw-r--r--lib/Target/Sparc/SparcV8JITInfo.h8
13 files changed, 83 insertions, 83 deletions
diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp
index 09937dea26..71dc022b9f 100644
--- a/lib/Target/Sparc/DelaySlotFiller.cpp
+++ b/lib/Target/Sparc/DelaySlotFiller.cpp
@@ -1,10 +1,10 @@
//===-- DelaySlotFiller.cpp - SparcV8 delay slot filler -------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This is a simple local pass that fills delay slots with NOPs.
diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp
index 49298c225b..c319833599 100644
--- a/lib/Target/Sparc/FPMover.cpp
+++ b/lib/Target/Sparc/FPMover.cpp
@@ -1,10 +1,10 @@
//===-- FPMover.cpp - SparcV8 double-precision floating point move fixer --===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Turns FpMOVD instructions into FMOVS pairs after regalloc.
diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h
index 5b820708ac..8c58dbfd3c 100644
--- a/lib/Target/Sparc/Sparc.h
+++ b/lib/Target/Sparc/Sparc.h
@@ -1,10 +1,10 @@
//===-- SparcV8.h - Top-level interface for SparcV8 representation -*- C++ -*-//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the entry points for global functions defined in the LLVM
diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp
index 71210536e7..3ce502f3cf 100644
--- a/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -1,10 +1,10 @@
//===-- SparcV8AsmPrinter.cpp - SparcV8 LLVM assembly writer --------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains a printer that converts from our internal representation
@@ -71,7 +71,7 @@ namespace {
void printOperand(const MachineInstr *MI, int opNum);
void printBaseOffsetPair (const MachineInstr *MI, int i, bool brackets=true);
void printMachineInstruction(const MachineInstr *MI);
- bool runOnMachineFunction(MachineFunction &F);
+ bool runOnMachineFunction(MachineFunction &F);
bool doInitialization(Module &M);
bool doFinalization(Module &M);
};
@@ -203,7 +203,7 @@ void V8Printer::emitConstantValueOnly(const Constant *CV) {
// Print a constant value or values, with the appropriate storage class as a
// prefix.
-void V8Printer::emitGlobalConstant(const Constant *CV) {
+void V8Printer::emitGlobalConstant(const Constant *CV) {
const TargetData &TD = TM.getTargetData();
if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) {
@@ -235,7 +235,7 @@ void V8Printer::emitGlobalConstant(const Constant *CV) {
// Insert the field padding unless it's zero bytes...
if (padSize)
- O << "\t.skip\t " << padSize << "\n";
+ O << "\t.skip\t " << padSize << "\n";
}
assert(sizeSoFar == cvsLayout->StructSize &&
"Layout of constant struct may be incorrect!");
@@ -268,7 +268,7 @@ void V8Printer::emitGlobalConstant(const Constant *CV) {
}
} else if (isa<UndefValue> (CV)) {
unsigned size = TD.getTypeSize (CV->getType ());
- O << "\t.skip\t " << size << "\n";
+ O << "\t.skip\t " << size << "\n";
return;
} else if (isa<ConstantAggregateZero> (CV)) {
unsigned size = TD.getTypeSize (CV->getType ());
@@ -311,7 +311,7 @@ void V8Printer::emitGlobalConstant(const Constant *CV) {
void V8Printer::printConstantPool(MachineConstantPool *MCP) {
const std::vector<Constant*> &CP = MCP->getConstants();
const TargetData &TD = TM.getTargetData();
-
+
if (CP.empty()) return;
for (unsigned i = 0, e = CP.size(); i != e; ++i) {
@@ -424,7 +424,7 @@ void V8Printer::printOperand(const MachineInstr *MI, int opNum) {
O << ".CPI" << CurrentFnName << "_" << MO.getConstantPoolIndex();
break;
default:
- O << "<unknown operand type>"; abort (); break;
+ O << "<unknown operand type>"; abort (); break;
}
if (CloseParen) O << ")";
}
@@ -511,7 +511,7 @@ void V8Printer::printMachineInstruction(const MachineInstr *MI) {
O << "! ";
O << Desc.Name << " ";
-
+
// Printing memory instructions is a special case.
// for loads: %dest = op %base, offset --> op [%base + offset], %dest
// for stores: op %base, offset, %src --> op %src, [%base + offset]
@@ -550,7 +550,7 @@ void V8Printer::printMachineInstruction(const MachineInstr *MI) {
for (unsigned i = 0; i < MI->getNumOperands (); ++i)
if (MI->getOperand (i).isRegister () && MI->getOperand (i).isDef ())
print_order.push_back (i);
- for (unsigned i = 0, e = print_order.size (); i != e; ++i) {
+ for (unsigned i = 0, e = print_order.size (); i != e; ++i) {
printOperand (MI, print_order[i]);
if (i != (print_order.size () - 1))
O << ", ";
@@ -588,13 +588,13 @@ bool V8Printer::doFinalization(Module &M) {
unsigned Size = TD.getTypeSize(C->getType());
unsigned Align = TD.getTypeAlignment(C->getType());
- if (C->isNullValue() &&
+ if (C->isNullValue() &&
(I->hasLinkOnceLinkage() || I->hasInternalLinkage() ||
I->hasWeakLinkage() /* FIXME: Verify correct */)) {
SwitchSection(O, CurSection, ".data");
if (I->hasInternalLinkage())
O << "\t.local " << name << "\n";
-
+
O << "\t.comm " << name << "," << TD.getTypeSize(C->getType())
<< "," << (unsigned)TD.getTypeAlignment(C->getType());
O << "\t\t! ";
@@ -609,7 +609,7 @@ bool V8Printer::doFinalization(Module &M) {
SwitchSection(O, CurSection, "");
O << "\t.section\t\".llvm.linkonce.d." << name << "\",\"aw\",@progbits\n";
break;
-
+
case GlobalValue::AppendingLinkage:
// FIXME: appending linkage variables should go into a section of
// their name or something. For now, just emit them as external.
diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp
index 6a60a66608..a5f5c1da9c 100644
--- a/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -1,10 +1,10 @@
//===- SparcV8InstrInfo.cpp - SparcV8 Instruction Information ---*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the TargetInstrInfo class.
diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h
index 9c7838dfdd..dc4cf0f65b 100644
--- a/lib/Target/Sparc/SparcInstrInfo.h
+++ b/lib/Target/Sparc/SparcInstrInfo.h
@@ -1,10 +1,10 @@
//===- SparcV8InstrInfo.h - SparcV8 Instruction Information -----*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the TargetInstrInfo class.
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index fe7aa2f879..5293d3fe1d 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -1,10 +1,10 @@
//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the MRegisterInfo class.
@@ -44,7 +44,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const TargetRegisterClass *RC = getClass(SrcReg);
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
- if (RC == SparcV8::IntRegsRegisterClass)
+ if (RC == SparcV8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
.addReg (SrcReg);
else if (RC == SparcV8::FPRegsRegisterClass)
@@ -61,7 +61,7 @@ void SparcV8RegisterInfo::
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FrameIdx) const {
const TargetRegisterClass *RC = getClass(DestReg);
- if (RC == SparcV8::IntRegsRegisterClass)
+ if (RC == SparcV8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
else if (RC == SparcV8::FPRegsRegisterClass)
BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
@@ -77,7 +77,7 @@ void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
- if (RC == SparcV8::IntRegsRegisterClass)
+ if (RC == SparcV8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
else if (RC == SparcV8::FPRegsRegisterClass)
BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h
index b53202edaf..851bd8038a 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.h
+++ b/lib/Target/Sparc/SparcRegisterInfo.h
@@ -1,10 +1,10 @@
//===- SparcV8RegisterInfo.h - SparcV8 Register Information Impl -*- C++ -*-==//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the MRegisterInfo class.
@@ -33,7 +33,7 @@ struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex) const;
-
+
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp
index 7f19114b55..cea6939393 100644
--- a/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -1,12 +1,12 @@
//===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
//
//===----------------------------------------------------------------------===//
@@ -87,7 +87,7 @@ bool SparcV8TargetMachine::addPassesToEmitAssembly(PassManager &PM,
// Print LLVM code input to instruction selector:
if (PrintMachineCode)
PM.add(new PrintFunctionPass());
-
+
PM.add(createSparcV8SimpleInstructionSelector(*this));
// Print machine instructions as they were initially generated.
@@ -126,7 +126,7 @@ void SparcV8JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
// Replace malloc and free instructions with library calls.
PM.add(createLowerAllocationsPass());
-
+
// FIXME: implement the switch instruction in the instruction selector.
PM.add(createLowerSwitchPass());
@@ -134,17 +134,17 @@ void SparcV8JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
PM.add(createLowerInvokePass());
PM.add(createLowerConstantExpressionsPass());
-
+
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
// FIXME: implement the select instruction in the instruction selector.
PM.add(createLowerSelectPass());
-
+
// Print LLVM code input to instruction selector:
if (PrintMachineCode)
PM.add(new PrintFunctionPass());
-
+
PM.add(createSparcV8SimpleInstructionSelector(TM));
// Print machine instructions as they were initially generated.
diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h
index 86bfa8d990..71c57aab10 100644
--- a/lib/Target/Sparc/SparcTargetMachine.h
+++ b/lib/Target/Sparc/SparcTargetMachine.h
@@ -1,12 +1,12 @@
//===-- SparcV8TargetMachine.h - Define TargetMachine for SparcV8 -*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file declares the SparcV8 specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
@@ -52,7 +52,7 @@ public:
///
virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE);
-
+
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
};
diff --git a/lib/Target/Sparc/SparcV8CodeEmitter.cpp b/lib/Target/Sparc/SparcV8CodeEmitter.cpp
index 76c854bc53..e0faba0d00 100644
--- a/lib/Target/Sparc/SparcV8CodeEmitter.cpp
+++ b/lib/Target/Sparc/SparcV8CodeEmitter.cpp
@@ -1,12 +1,12 @@
//===-- SparcV8CodeEmitter.cpp - JIT Code Emitter for SparcV8 -----*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
//
//===----------------------------------------------------------------------===//
@@ -78,7 +78,7 @@ bool SparcV8TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE) {
// Keep as `true' until this is a functional JIT to allow llvm-gcc to build
return true;
-
+
// Machine code emitter pass for SparcV8
PM.add(new SparcV8CodeEmitter(*this, MCE));
// Delete machine code for this function after emitting it
diff --git a/lib/Target/Sparc/SparcV8ISelSimple.cpp b/lib/Target/Sparc/SparcV8ISelSimple.cpp
index 633236883d..0fa06e5e7f 100644
--- a/lib/Target/Sparc/SparcV8ISelSimple.cpp
+++ b/lib/Target/Sparc/SparcV8ISelSimple.cpp
@@ -1,10 +1,10 @@
//===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines a simple peephole instruction selector for the V8 target
@@ -318,7 +318,7 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
} else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
// Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
- // that SETHI %reg,global == SETHI %reg,%hi(global) and
+ // that SETHI %reg,global == SETHI %reg,%hi(global) and
// OR %reg,global,%reg == OR %reg,%lo(global),%reg.
unsigned TmpReg = makeAnotherReg (C->getType ());
BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress(GV);
@@ -362,10 +362,10 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
const unsigned *IAR = &IncomingArgRegs[0];
unsigned ArgOffset = 68;
- // Store registers onto stack if this is a varargs function.
+ // Store registers onto stack if this is a varargs function.
// FIXME: This doesn't really pertain to "loading arguments into
// virtual registers", so it's not clear that it really belongs here.
- // FIXME: We could avoid storing any args onto the stack that don't
+ // FIXME: We could avoid storing any args onto the stack that don't
// need to be in memory, because they come before the ellipsis in the
// parameter list (and thus could never be accessed through va_arg).
if (LF->getFunctionType ()->isVarArg ()) {
@@ -505,7 +505,7 @@ void V8ISel::SelectPHINodes() {
break;
}
assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
-
+
unsigned ValReg;
std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
PHIValues.lower_bound(PredMBB);
@@ -515,7 +515,7 @@ void V8ISel::SelectPHINodes() {
// predecessor. Recycle it.
ValReg = EntryIt->second;
- } else {
+ } else {
// Get the incoming value into a virtual register.
//
Value *Val = PN->getIncomingValue(i);
@@ -534,11 +534,11 @@ void V8ISel::SelectPHINodes() {
// might be arbitrarily complex if it is a constant expression),
// just insert the computation at the top of the basic block.
MachineBasicBlock::iterator PI = PredMBB->begin();
-
+
// Skip over any PHI nodes though!
while (PI != PredMBB->end() && PI->getOpcode() == V8::PHI)
++PI;
-
+
ValReg = getReg(Val, PredMBB, PI);
}
@@ -568,28 +568,28 @@ bool V8ISel::runOnFunction(Function &Fn) {
// First pass over the function, lower any unknown intrinsic functions
// with the IntrinsicLowering class.
LowerUnknownIntrinsicFunctionCalls(Fn);
-
+
F = &MachineFunction::construct(&Fn, TM);
-
+
// Create all of the machine basic blocks for the function...
for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
-
+
BB = &F->front();
-
+
// Set up a frame object for the return address. This is used by the
// llvm.returnaddress & llvm.frameaddress intrinisics.
//ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
-
+
// Copy incoming arguments off of the stack and out of fixed registers.
LoadArgumentsToVirtualRegs(&Fn);
-
+
// Instruction select everything except PHI nodes
visit(Fn);
-
+
// Select the PHI nodes
SelectPHINodes();
-
+
RegMap.clear();
MBBMap.clear();
F = 0;
@@ -632,11 +632,11 @@ void V8ISel::emitFPToIntegerCast (MachineBasicBlock *BB,
const Type *newTy, unsigned DestReg) {
unsigned FPCastOpcode, FPStoreOpcode, FPSize, FPAlign;
unsigned oldTyClass = getClassB(oldTy);
- if (oldTyClass == cFloat) {
- FPCastOpcode = V8::FSTOI; FPStoreOpcode = V8::STFri; FPSize = 4;
+ if (oldTyClass == cFloat) {
+ FPCastOpcode = V8::FSTOI; FPStoreOpcode = V8::STFri; FPSize = 4;
FPAlign = TM.getTargetData().getFloatAlignment();
} else { // it's a double
- FPCastOpcode = V8::FDTOI; FPStoreOpcode = V8::STDFri; FPSize = 8;
+ FPCastOpcode = V8::FDTOI; FPStoreOpcode = V8::STDFri; FPSize = 8;
FPAlign = TM.getTargetData().getDoubleAlignment();
}
unsigned TempReg = makeAnotherReg (oldTy);
@@ -672,11 +672,11 @@ void V8ISel::emitCastOperation(MachineBasicBlock *BB,
case cShort:
case cInt:
switch (oldTyClass) {
- case cLong:
+ case cLong:
// Treat it like a cast from the lower half of the value.
emitIntegerCast (BB, IP, Type::IntTy, SrcReg+1, newTy, DestReg);
break;
- case cFloat:
+ case cFloat:
case cDouble:
emitFPToIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
break;
@@ -742,10 +742,10 @@ void V8ISel::emitCastOperation(MachineBasicBlock *BB,
unsigned TempReg = emitIntegerCast (BB, IP, OldHalfTy, SrcReg,
NewHalfTy, DestReg+1, true);
if (newTy->isSigned ()) {
- BuildMI (*BB, IP, V8::SRAri, 2, DestReg).addReg (TempReg)
+ BuildMI (*BB, IP, V8::SRAri, 2, DestReg).addReg (TempReg)
.addZImm (31);
} else {
- BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0)
+ BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0)
.addReg (V8::G0);
}
break;
@@ -1162,7 +1162,7 @@ void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
if (isa<ConstantIntegral> (idx)) {
// If idx is a constant, we don't have to emit the multiply.
int64_t Val = cast<ConstantIntegral> (idx)->getRawValue ();
- if ((Val * elementSize) + 4096 < 8191) {
+ if ((Val * elementSize) + 4096 < 8191) {
// (Val * elementSize) is constant and fits in an immediate field.
// emit: nextBasePtrReg = ADDri basePtrReg, (Val * elementSize)
addImmed = true;
@@ -1180,16 +1180,16 @@ void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
OffsetReg = makeAnotherReg (Type::IntTy);
unsigned idxReg = getReg (idx, MBB, IP);
switch (elementSize) {
- case 1:
+ case 1:
BuildMI (*MBB, IP, V8::ORrr, 2, OffsetReg).addReg (V8::G0).addReg (idxReg);
break;
- case 2:
+ case 2:
BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (1);
break;
- case 4:
+ case 4:
BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (2);
break;
- case 8:
+ case 8:
BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (3);
break;
default: {
@@ -1343,7 +1343,7 @@ void V8ISel::emitShift64 (MachineBasicBlock *MBB,
// ba .lshr_continue
BB = oneShiftMBB;
-
+
if (isSigned)
BuildMI (BB, V8::SRAri, 2, OneShiftOutReg).addReg (SrcReg).addZImm (31);
else
@@ -1515,7 +1515,7 @@ void V8ISel::visitBinaryOperator (Instruction &I) {
}
switch (getClassB (I.getType ())) {
- case cByte:
+ case cByte:
if (I.getType ()->isSigned ()) { // add byte
BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
} else { // add ubyte
@@ -1562,7 +1562,7 @@ void V8ISel::visitSetCondInst(SetCondInst &I) {
unsigned Op1Reg = getReg (I.getOperand (1));
unsigned DestReg = getReg (I);
const Type *Ty = I.getOperand (0)->getType ();
-
+
// Compare the two values.
if (getClass (Ty) < cLong) {
BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
diff --git a/lib/Target/Sparc/SparcV8JITInfo.h b/lib/Target/Sparc/SparcV8JITInfo.h
index db866a0af7..b17eb3db6d 100644
--- a/lib/Target/Sparc/SparcV8JITInfo.h
+++ b/lib/Target/Sparc/SparcV8JITInfo.h
@@ -1,10 +1,10 @@
//===- SparcV8JITInfo.h - SparcV8 impl. of the JIT interface ----*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV8 implementation of the TargetJITInfo class.
@@ -30,14 +30,14 @@ namespace llvm {
/// is not supported for this target.
///
virtual void addPassesToJITCompile(FunctionPassManager &PM);
-
+
/// replaceMachineCodeForFunction - Make it so that calling the function
/// whose machine code is at OLD turns into a call to NEW, perhaps by
/// overwriting OLD with a branch to NEW. This is used for self-modifying
/// code.
///
virtual void replaceMachineCodeForFunction(void *Old, void *New);
-
+
/// getJITStubForFunction - Create or return a stub for the specified
/// function. This stub acts just like the specified function, except that
/// it allows the "address" of the function to be taken without having to
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-04-28 02:42:23 +0000