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-rw-r--r--lib/Target/Sparc/DelaySlotFiller.cpp37
-rw-r--r--lib/Target/Sparc/FPMover.cpp46
-rw-r--r--lib/Target/Sparc/Makefile14
-rw-r--r--lib/Target/Sparc/Sparc.h89
-rw-r--r--lib/Target/Sparc/Sparc.td12
-rw-r--r--lib/Target/Sparc/SparcAsmPrinter.cpp48
-rw-r--r--lib/Target/Sparc/SparcISelDAGToDAG.cpp350
-rw-r--r--lib/Target/Sparc/SparcInstrFormats.td16
-rw-r--r--lib/Target/Sparc/SparcInstrInfo.cpp50
-rw-r--r--lib/Target/Sparc/SparcInstrInfo.h20
-rw-r--r--lib/Target/Sparc/SparcInstrInfo.td148
-rw-r--r--lib/Target/Sparc/SparcRegisterInfo.cpp132
-rw-r--r--lib/Target/Sparc/SparcRegisterInfo.h18
-rw-r--r--lib/Target/Sparc/SparcRegisterInfo.td16
-rw-r--r--lib/Target/Sparc/SparcSubtarget.cpp8
-rw-r--r--lib/Target/Sparc/SparcSubtarget.h6
-rw-r--r--lib/Target/Sparc/SparcTargetMachine.cpp36
-rw-r--r--lib/Target/Sparc/SparcTargetMachine.h24
18 files changed, 532 insertions, 538 deletions
diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp
index 71dc022b9f..2ef8ffef80 100644
--- a/lib/Target/Sparc/DelaySlotFiller.cpp
+++ b/lib/Target/Sparc/DelaySlotFiller.cpp
@@ -1,4 +1,4 @@
-//===-- DelaySlotFiller.cpp - SparcV8 delay slot filler -------------------===//
+//===-- DelaySlotFiller.cpp - SPARC delay slot filler ---------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -11,17 +11,16 @@
//
//===----------------------------------------------------------------------===//
-#include "SparcV8.h"
+#include "Sparc.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/ADT/Statistic.h"
-
using namespace llvm;
namespace {
- Statistic<> FilledSlots ("delayslotfiller", "Num. of delay slots filled");
+ Statistic<> FilledSlots("delayslotfiller", "Num. of delay slots filled");
struct Filler : public MachineFunctionPass {
/// Target machine description which we query for reg. names, data
@@ -30,42 +29,42 @@ namespace {
TargetMachine &TM;
const TargetInstrInfo *TII;
- Filler (TargetMachine &tm) : TM (tm), TII (tm.getInstrInfo ()) { }
+ Filler(TargetMachine &tm) : TM(tm), TII(tm.getInstrInfo()) { }
- virtual const char *getPassName () const {
- return "SparcV8 Delay Slot Filler";
+ virtual const char *getPassName() const {
+ return "SPARC Delay Slot Filler";
}
- bool runOnMachineBasicBlock (MachineBasicBlock &MBB);
- bool runOnMachineFunction (MachineFunction &F) {
+ bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
+ bool runOnMachineFunction(MachineFunction &F) {
bool Changed = false;
- for (MachineFunction::iterator FI = F.begin (), FE = F.end ();
+ for (MachineFunction::iterator FI = F.begin(), FE = F.end();
FI != FE; ++FI)
- Changed |= runOnMachineBasicBlock (*FI);
+ Changed |= runOnMachineBasicBlock(*FI);
return Changed;
}
};
} // end of anonymous namespace
-/// createSparcV8DelaySlotFillerPass - Returns a pass that fills in delay
-/// slots in SparcV8 MachineFunctions
+/// createSparcDelaySlotFillerPass - Returns a pass that fills in delay
+/// slots in Sparc MachineFunctions
///
-FunctionPass *llvm::createSparcV8DelaySlotFillerPass (TargetMachine &tm) {
- return new Filler (tm);
+FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
+ return new Filler(tm);
}
/// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
/// Currently, we fill delay slots with NOPs. We assume there is only one
/// delay slot per delayed instruction.
///
-bool Filler::runOnMachineBasicBlock (MachineBasicBlock &MBB) {
+bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool Changed = false;
- for (MachineBasicBlock::iterator I = MBB.begin (); I != MBB.end (); ++I)
- if (TII->hasDelaySlot (I->getOpcode ())) {
+ for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
+ if (TII->hasDelaySlot(I->getOpcode())) {
MachineBasicBlock::iterator J = I;
++J;
- BuildMI (MBB, J, V8::NOP, 0);
+ BuildMI(MBB, J, SP::NOP, 0);
++FilledSlots;
Changed = true;
}
diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp
index 8bc1009d37..70f203ccca 100644
--- a/lib/Target/Sparc/FPMover.cpp
+++ b/lib/Target/Sparc/FPMover.cpp
@@ -1,4 +1,4 @@
-//===-- FPMover.cpp - SparcV8 double-precision floating point move fixer --===//
+//===-- FPMover.cpp - Sparc double-precision floating point move fixer ----===//
//
// The LLVM Compiler Infrastructure
//
@@ -11,8 +11,8 @@
//
//===----------------------------------------------------------------------===//
-#include "SparcV8.h"
-#include "SparcV8Subtarget.h"
+#include "Sparc.h"
+#include "SparcSubtarget.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/TargetMachine.h"
@@ -34,7 +34,7 @@ namespace {
FPMover(TargetMachine &tm) : TM(tm) { }
virtual const char *getPassName() const {
- return "SparcV8 Double-FP Move Fixer";
+ return "Sparc Double-FP Move Fixer";
}
bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
@@ -42,10 +42,10 @@ namespace {
};
} // end of anonymous namespace
-/// createSparcV8FPMoverPass - Returns a pass that turns FpMOVD
+/// createSparcFPMoverPass - Returns a pass that turns FpMOVD
/// instructions into FMOVS instructions
///
-FunctionPass *llvm::createSparcV8FPMoverPass(TargetMachine &tm) {
+FunctionPass *llvm::createSparcFPMoverPass(TargetMachine &tm) {
return new FPMover(tm);
}
@@ -54,16 +54,16 @@ FunctionPass *llvm::createSparcV8FPMoverPass(TargetMachine &tm) {
static void getDoubleRegPair(unsigned DoubleReg, unsigned &EvenReg,
unsigned &OddReg) {
static const unsigned EvenHalvesOfPairs[] = {
- V8::F0, V8::F2, V8::F4, V8::F6, V8::F8, V8::F10, V8::F12, V8::F14,
- V8::F16, V8::F18, V8::F20, V8::F22, V8::F24, V8::F26, V8::F28, V8::F30
+ SP::F0, SP::F2, SP::F4, SP::F6, SP::F8, SP::F10, SP::F12, SP::F14,
+ SP::F16, SP::F18, SP::F20, SP::F22, SP::F24, SP::F26, SP::F28, SP::F30
};
static const unsigned OddHalvesOfPairs[] = {
- V8::F1, V8::F3, V8::F5, V8::F7, V8::F9, V8::F11, V8::F13, V8::F15,
- V8::F17, V8::F19, V8::F21, V8::F23, V8::F25, V8::F27, V8::F29, V8::F31
+ SP::F1, SP::F3, SP::F5, SP::F7, SP::F9, SP::F11, SP::F13, SP::F15,
+ SP::F17, SP::F19, SP::F21, SP::F23, SP::F25, SP::F27, SP::F29, SP::F31
};
static const unsigned DoubleRegsInOrder[] = {
- V8::D0, V8::D1, V8::D2, V8::D3, V8::D4, V8::D5, V8::D6, V8::D7, V8::D8,
- V8::D9, V8::D10, V8::D11, V8::D12, V8::D13, V8::D14, V8::D15
+ SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8,
+ SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15
};
for (unsigned i = 0; i < sizeof(DoubleRegsInOrder)/sizeof(unsigned); ++i)
if (DoubleRegsInOrder[i] == DoubleReg) {
@@ -80,12 +80,12 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
MachineInstr *MI = I++;
- if (MI->getOpcode() == V8::FpMOVD || MI->getOpcode() == V8::FpABSD ||
- MI->getOpcode() == V8::FpNEGD) {
+ if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD ||
+ MI->getOpcode() == SP::FpNEGD) {
Changed = true;
unsigned DestDReg = MI->getOperand(0).getReg();
unsigned SrcDReg = MI->getOperand(1).getReg();
- if (DestDReg == SrcDReg && MI->getOpcode() == V8::FpMOVD) {
+ if (DestDReg == SrcDReg && MI->getOpcode() == SP::FpMOVD) {
MBB.erase(MI); // Eliminate the noop copy.
++NoopFpDs;
continue;
@@ -95,12 +95,12 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
getDoubleRegPair(DestDReg, EvenDestReg, OddDestReg);
getDoubleRegPair(SrcDReg, EvenSrcReg, OddSrcReg);
- if (MI->getOpcode() == V8::FpMOVD)
- MI->setOpcode(V8::FMOVS);
- else if (MI->getOpcode() == V8::FpNEGD)
- MI->setOpcode(V8::FNEGS);
- else if (MI->getOpcode() == V8::FpABSD)
- MI->setOpcode(V8::FABSS);
+ if (MI->getOpcode() == SP::FpMOVD)
+ MI->setOpcode(SP::FMOVS);
+ else if (MI->getOpcode() == SP::FpNEGD)
+ MI->setOpcode(SP::FNEGS);
+ else if (MI->getOpcode() == SP::FpABSD)
+ MI->setOpcode(SP::FABSS);
else
assert(0 && "Unknown opcode!");
@@ -109,7 +109,7 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI);
// Insert copy for the other half of the double.
if (DestDReg != SrcDReg) {
- MI = BuildMI(MBB, I, V8::FMOVS, 1, OddDestReg).addReg(OddSrcReg);
+ MI = BuildMI(MBB, I, SP::FMOVS, 1, OddDestReg).addReg(OddSrcReg);
DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI);
}
++NumFpDs;
@@ -121,7 +121,7 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool FPMover::runOnMachineFunction(MachineFunction &F) {
// If the target has V9 instructions, the fp-mover pseudos will never be
// emitted. Avoid a scan of the instructions to improve compile time.
- if (TM.getSubtarget<SparcV8Subtarget>().isV9())
+ if (TM.getSubtarget<SparcSubtarget>().isV9())
return false;
bool Changed = false;
diff --git a/lib/Target/Sparc/Makefile b/lib/Target/Sparc/Makefile
index 7d61984048..8cc4add374 100644
--- a/lib/Target/Sparc/Makefile
+++ b/lib/Target/Sparc/Makefile
@@ -1,4 +1,4 @@
-##===- lib/Target/SparcV8/Makefile -------------------------*- Makefile -*-===##
+##===- lib/Target/Sparc/Makefile ---------------------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
@@ -7,14 +7,14 @@
#
##===----------------------------------------------------------------------===##
LEVEL = ../../..
-LIBRARYNAME = LLVMSparcV8
-TARGET = SparcV8
+LIBRARYNAME = LLVMSparc
+TARGET = Sparc
# Make sure that tblgen is run, first thing.
-BUILT_SOURCES = SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
- SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
- SparcV8GenInstrInfo.inc SparcV8GenAsmWriter.inc \
- SparcV8GenDAGISel.inc SparcV8GenSubtarget.inc
+BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \
+ SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
+ SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
+ SparcGenDAGISel.inc SparcGenSubtarget.inc
include $(LEVEL)/Makefile.common
diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h
index faf160b16c..084bfe3987 100644
--- a/lib/Target/Sparc/Sparc.h
+++ b/lib/Target/Sparc/Sparc.h
@@ -1,4 +1,4 @@
-//===-- SparcV8.h - Top-level interface for SparcV8 representation -*- C++ -*-//
+//===-- Sparc.h - Top-level interface for Sparc representation --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -8,43 +8,40 @@
//===----------------------------------------------------------------------===//
//
// This file contains the entry points for global functions defined in the LLVM
-// SparcV8 back-end.
+// Sparc back-end.
//
//===----------------------------------------------------------------------===//
-#ifndef TARGET_SPARCV8_H
-#define TARGET_SPARCV8_H
+#ifndef TARGET_SPARC_H
+#define TARGET_SPARC_H
#include <iosfwd>
#include <cassert>
namespace llvm {
-
class FunctionPass;
class TargetMachine;
- FunctionPass *createSparcV8ISelDag(TargetMachine &TM);
-
- FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
- TargetMachine &TM);
- FunctionPass *createSparcV8DelaySlotFillerPass(TargetMachine &TM);
- FunctionPass *createSparcV8FPMoverPass(TargetMachine &TM);
+ FunctionPass *createSparcISelDag(TargetMachine &TM);
+ FunctionPass *createSparcCodePrinterPass(std::ostream &OS, TargetMachine &TM);
+ FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
+ FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
} // end namespace llvm;
-// Defines symbolic names for SparcV8 registers. This defines a mapping from
+// Defines symbolic names for Sparc registers. This defines a mapping from
// register name to register number.
//
-#include "SparcV8GenRegisterNames.inc"
+#include "SparcGenRegisterNames.inc"
-// Defines symbolic names for the SparcV8 instructions.
+// Defines symbolic names for the Sparc instructions.
//
-#include "SparcV8GenInstrNames.inc"
+#include "SparcGenInstrNames.inc"
namespace llvm {
- // Enums corresponding to SparcV8 condition codes, both icc's and fcc's. These
+ // Enums corresponding to Sparc condition codes, both icc's and fcc's. These
// values must be kept in sync with the ones in the .td file.
- namespace V8CC {
+ namespace SPCC {
enum CondCodes {
//ICC_A = 8 , // Always
//ICC_N = 0 , // Never
@@ -82,37 +79,37 @@ namespace llvm {
};
}
- static const char *SPARCCondCodeToString(V8CC::CondCodes CC) {
+ static const char *SPARCCondCodeToString(SPCC::CondCodes CC) {
switch (CC) {
default: assert(0 && "Unknown condition code");
- case V8CC::ICC_NE: return "ne";
- case V8CC::ICC_E: return "e";
- case V8CC::ICC_G: return "g";
- case V8CC::ICC_LE: return "le";
- case V8CC::ICC_GE: return "ge";
- case V8CC::ICC_L: return "l";
- case V8CC::ICC_GU: return "gu";
- case V8CC::ICC_LEU: return "leu";
- case V8CC::ICC_CC: return "cc";
- case V8CC::ICC_CS: return "cs";
- case V8CC::ICC_POS: return "pos";
- case V8CC::ICC_NEG: return "neg";
- case V8CC::ICC_VC: return "vc";
- case V8CC::ICC_VS: return "vs";
- case V8CC::FCC_U: return "u";
- case V8CC::FCC_G: return "g";
- case V8CC::FCC_UG: return "ug";
- case V8CC::FCC_L: return "l";
- case V8CC::FCC_UL: return "ul";
- case V8CC::FCC_LG: return "lg";
- case V8CC::FCC_NE: return "ne";
- case V8CC::FCC_E: return "e";
- case V8CC::FCC_UE: return "ue";
- case V8CC::FCC_GE: return "ge";
- case V8CC::FCC_UGE: return "uge";
- case V8CC::FCC_LE: return "le";
- case V8CC::FCC_ULE: return "ule";
- case V8CC::FCC_O: return "o";
+ case SPCC::ICC_NE: return "ne";
+ case SPCC::ICC_E: return "e";
+ case SPCC::ICC_G: return "g";
+ case SPCC::ICC_LE: return "le";
+ case SPCC::ICC_GE: return "ge";
+ case SPCC::ICC_L: return "l";
+ case SPCC::ICC_GU: return "gu";
+ case SPCC::ICC_LEU: return "leu";
+ case SPCC::ICC_CC: return "cc";
+ case SPCC::ICC_CS: return "cs";
+ case SPCC::ICC_POS: return "pos";
+ case SPCC::ICC_NEG: return "neg";
+ case SPCC::ICC_VC: return "vc";
+ case SPCC::ICC_VS: return "vs";
+ case SPCC::FCC_U: return "u";
+ case SPCC::FCC_G: return "g";
+ case SPCC::FCC_UG: return "ug";
+ case SPCC::FCC_L: return "l";
+ case SPCC::FCC_UL: return "ul";
+ case SPCC::FCC_LG: return "lg";
+ case SPCC::FCC_NE: return "ne";
+ case SPCC::FCC_E: return "e";
+ case SPCC::FCC_UE: return "ue";
+ case SPCC::FCC_GE: return "ge";
+ case SPCC::FCC_UGE: return "uge";
+ case SPCC::FCC_LE: return "le";
+ case SPCC::FCC_ULE: return "ule";
+ case SPCC::FCC_O: return "o";
}
}
} // end namespace llvm
diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td
index b123930157..aa8b9e2c72 100644
--- a/lib/Target/Sparc/Sparc.td
+++ b/lib/Target/Sparc/Sparc.td
@@ -1,4 +1,4 @@
-//===- SparcV8.td - Describe the SparcV8 Target Machine ---------*- C++ -*-===//
+//===- Sparc.td - Describe the Sparc Target Machine -------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -34,15 +34,15 @@ def FeatureVIS
// Register File Description
//===----------------------------------------------------------------------===//
-include "SparcV8RegisterInfo.td"
+include "SparcRegisterInfo.td"
//===----------------------------------------------------------------------===//
// Instruction Descriptions
//===----------------------------------------------------------------------===//
-include "SparcV8InstrInfo.td"
+include "SparcInstrInfo.td"
-def SparcV8InstrInfo : InstrInfo {
+def SparcInstrInfo : InstrInfo {
// Define how we want to layout our target-specific information field.
let TSFlagsFields = [];
let TSFlagsShifts = [];
@@ -74,7 +74,7 @@ def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
-def SparcV8 : Target {
+def Sparc : Target {
// Pointers are 32-bits in size.
let PointerType = i32;
@@ -82,5 +82,5 @@ def SparcV8 : Target {
let CalleeSavedRegisters = [];
// Pull in Instruction Info:
- let InstructionSet = SparcV8InstrInfo;
+ let InstructionSet = SparcInstrInfo;
}
diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp
index dd1b46904d..2e88db6305 100644
--- a/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -1,4 +1,4 @@
-//===-- SparcV8AsmPrinter.cpp - SparcV8 LLVM assembly writer --------------===//
+//===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -8,12 +8,12 @@
//===----------------------------------------------------------------------===//
//
// This file contains a printer that converts from our internal representation
-// of machine-dependent LLVM code to GAS-format Sparc V8 assembly language.
+// of machine-dependent LLVM code to GAS-format SPARC assembly language.
//
//===----------------------------------------------------------------------===//
-#include "SparcV8.h"
-#include "SparcV8InstrInfo.h"
+#include "Sparc.h"
+#include "SparcInstrInfo.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Module.h"
@@ -35,8 +35,8 @@ using namespace llvm;
namespace {
Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
- struct SparcV8AsmPrinter : public AsmPrinter {
- SparcV8AsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) {
+ struct SparcAsmPrinter : public AsmPrinter {
+ SparcAsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) {
Data16bitsDirective = "\t.half\t";
Data32bitsDirective = "\t.word\t";
Data64bitsDirective = 0; // .xword is only supported by V9.
@@ -53,12 +53,12 @@ namespace {
ValueMapTy NumberForBB;
virtual const char *getPassName() const {
- return "SparcV8 Assembly Printer";
+ return "Sparc Assembly Printer";
}
void printOperand(const MachineInstr *MI, int opNum);
void printMemOperand(const MachineInstr *MI, int opNum);
- void printV8CCOperand(const MachineInstr *MI, int opNum);
+ void printCCOperand(const MachineInstr *MI, int opNum);
bool printInstruction(const MachineInstr *MI); // autogenerated.
bool runOnMachineFunction(MachineFunction &F);
@@ -67,22 +67,22 @@ namespace {
};
} // end of anonymous namespace
-#include "SparcV8GenAsmWriter.inc"
+#include "SparcGenAsmWriter.inc"
-/// createSparcV8CodePrinterPass - Returns a pass that prints the SparcV8
+/// createSparcCodePrinterPass - Returns a pass that prints the SPARC
/// assembly code for a MachineFunction to the given output stream,
/// using the given target machine description. This should work
/// regardless of whether the function is in SSA form.
///
-FunctionPass *llvm::createSparcV8CodePrinterPass (std::ostream &o,
- TargetMachine &tm) {
- return new SparcV8AsmPrinter(o, tm);
+FunctionPass *llvm::createSparcCodePrinterPass(std::ostream &o,
+ TargetMachine &tm) {
+ return new SparcAsmPrinter(o, tm);
}
/// runOnMachineFunction - This uses the printMachineInstruction()
/// method to print assembly for each instruction.
///
-bool SparcV8AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
+bool SparcAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
SetupMachineFunction(MF);
// Print out constants referenced by the function
@@ -132,14 +132,14 @@ bool SparcV8AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
return false;
}
-void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
+void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
const MachineOperand &MO = MI->getOperand (opNum);
const MRegisterInfo &RI = *TM.getRegisterInfo();
bool CloseParen = false;
- if (MI->getOpcode() == V8::SETHIi && !MO.isRegister() && !MO.isImmediate()) {
+ if (MI->getOpcode() == SP::SETHIi && !MO.isRegister() && !MO.isImmediate()) {
O << "%hi(";
CloseParen = true;
- } else if ((MI->getOpcode() == V8::ORri || MI->getOpcode() == V8::ADDri)
+ } else if ((MI->getOpcode() == SP::ORri || MI->getOpcode() == SP::ADDri)
&& !MO.isRegister() && !MO.isImmediate()) {
O << "%lo(";
CloseParen = true;
@@ -170,7 +170,7 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
return;
}
case MachineOperand::MO_PCRelativeDisp:
- std::cerr << "Shouldn't use addPCDisp() when building SparcV8 MachineInstrs";
+ std::cerr << "Shouldn't use addPCDisp() when building Sparc MachineInstrs";
abort ();
return;
case MachineOperand::MO_GlobalAddress:
@@ -189,13 +189,13 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
if (CloseParen) O << ")";
}
-void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
+void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
printOperand(MI, opNum);
MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
if ((OpTy == MachineOperand::MO_VirtualRegister ||
OpTy == MachineOperand::MO_MachineRegister) &&
- MI->getOperand(opNum+1).getReg() == V8::G0)
+ MI->getOperand(opNum+1).getReg() == SP::G0)
return; // don't print "+%g0"
if ((OpTy == MachineOperand::MO_SignExtendedImmed ||
OpTy == MachineOperand::MO_UnextendedImmed) &&
@@ -213,19 +213,19 @@ void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
}
}
-void SparcV8AsmPrinter::printV8CCOperand(const MachineInstr *MI, int opNum) {
+void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) {
int CC = (int)MI->getOperand(opNum).getImmedValue();
- O << SPARCCondCodeToString((V8CC::CondCodes)CC);
+ O << SPARCCondCodeToString((SPCC::CondCodes)CC);
}
-bool SparcV8AsmPrinter::doInitialization(Module &M) {
+bool SparcAsmPrinter::doInitialization(Module &M) {
Mang = new Mangler(M);
return false; // success
}
-bool SparcV8AsmPrinter::doFinalization(Module &M) {
+bool SparcAsmPrinter::doFinalization(Module &M) {
const TargetData &TD = TM.getTargetData();
// Print out module-level global variables here.
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index bd5073d897..8cae848bb0 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -1,4 +1,4 @@
-//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
+//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,12 +7,12 @@
//
//===----------------------------------------------------------------------===//
//
-// This file defines an instruction selector for the V8 target
+// This file defines an instruction selector for the SPARC target.
//
//===----------------------------------------------------------------------===//
-#include "SparcV8.h"
-#include "SparcV8TargetMachine.h"
+#include "Sparc.h"
+#include "SparcTargetMachine.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -30,9 +30,9 @@ using namespace llvm;
// TargetLowering Implementation
//===----------------------------------------------------------------------===//
-namespace V8ISD {
+namespace SPISD {
enum {
- FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
+ FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
CMPICC, // Compare two GPR operands, set icc.
CMPFCC, // Compare two FP operands, set fcc.
BRICC, // Branch to dest on icc condition
@@ -45,56 +45,56 @@ namespace V8ISD {
FTOI, // FP to Int within a FP register.
ITOF, // Int to FP within a FP register.
- CALL, // A V8 call instruction.
+ CALL, // A call instruction.
RET_FLAG, // Return with a flag operand.
};
}
/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
/// condition.
-static V8CC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
+static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
switch (CC) {
default: assert(0 && "Unknown integer condition code!");
- case ISD::SETEQ: return V8CC::ICC_E;
- case ISD::SETNE: return V8CC::ICC_NE;
- case ISD::SETLT: return V8CC::ICC_L;
- case ISD::SETGT: return V8CC::ICC_G;
- case ISD::SETLE: return V8CC::ICC_LE;
- case ISD::SETGE: return V8CC::ICC_GE;
- case ISD::SETULT: return V8CC::ICC_CS;
- case ISD::SETULE: return V8CC::ICC_LEU;
- case ISD::SETUGT: return V8CC::ICC_GU;
- case ISD::SETUGE: return V8CC::ICC_CC;
+ case ISD::SETEQ: return SPCC::ICC_E;
+ case ISD::SETNE: return SPCC::ICC_NE;
+ case ISD::SETLT: return SPCC::ICC_L;
+ case ISD::SETGT: return SPCC::ICC_G;
+ case ISD::SETLE: return SPCC::ICC_LE;
+ case ISD::SETGE: return SPCC::ICC_GE;
+ case ISD::SETULT: return SPCC::ICC_CS;
+ case ISD::SETULE: return SPCC::ICC_LEU;
+ case ISD::SETUGT: return SPCC::ICC_GU;
+ case ISD::SETUGE: return SPCC::ICC_CC;
}
}
/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
/// FCC condition.
-static V8CC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
+static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
switch (CC) {
default: assert(0 && "Unknown fp condition code!");
- case ISD::SETEQ: return V8CC::FCC_E;
- case ISD::SETNE: return V8CC::FCC_NE;
- case ISD::SETLT: return V8CC::FCC_L;
- case ISD::SETGT: return V8CC::FCC_G;
- case ISD::SETLE: return V8CC::FCC_LE;
- case ISD::SETGE: return V8CC::FCC_GE;
- case ISD::SETULT: return V8CC::FCC_UL;
- case ISD::SETULE: return V8CC::FCC_ULE;
- case ISD::SETUGT: return V8CC::FCC_UG;
- case ISD::SETUGE: return V8CC::FCC_UGE;
- case ISD::SETUO: return V8CC::FCC_U;
- case ISD::SETO: return V8CC::FCC_O;
- case ISD::SETONE: return V8CC::FCC_LG;
- case ISD::SETUEQ: return V8CC::FCC_UE;
+ case ISD::SETEQ: return SPCC::FCC_E;
+ case ISD::SETNE: return SPCC::FCC_NE;
+ case ISD::SETLT: return SPCC::FCC_L;
+ case ISD::SETGT: return SPCC::FCC_G;
+ case ISD::SETLE: return SPCC::FCC_LE;
+ case ISD::SETGE: return SPCC::FCC_GE;
+ case ISD::SETULT: return SPCC::FCC_UL;
+ case ISD::SETULE: return SPCC::FCC_ULE;
+ case ISD::SETUGT: return SPCC::FCC_UG;
+ case ISD::SETUGE: return SPCC::FCC_UGE;
+ case ISD::SETUO: return SPCC::FCC_U;
+ case ISD::SETO: return SPCC::FCC_O;
+ case ISD::SETONE: return SPCC::FCC_LG;
+ case ISD::SETUEQ: return SPCC::FCC_UE;
}
}
namespace {
- class SparcV8TargetLowering : public TargetLowering {
+ class SparcTargetLowering : public TargetLowering {
int VarArgsFrameOffset; // Frame offset to start of varargs area.
public:
- SparcV8TargetLowering(TargetMachine &TM);
+ SparcTargetLowering(TargetMachine &TM);
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
@@ -120,13 +120,13 @@ namespace {
};
}
-SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
+SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
: TargetLowering(TM) {
// Set up the register classes.
- addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
- addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
- addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
+ addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
+ addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
+ addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
// Custom legalize GlobalAddress nodes into LO/HI parts.
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
@@ -175,7 +175,7 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
- // V8 has no intrinsics for these particular operations.
+ // SPARC has no intrinsics for these particular operations.
setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
setOperationAction(ISD::MEMSET, MVT::Other, Expand);
setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
@@ -218,42 +218,42 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
- setStackPointerRegisterToSaveRestore(V8::O6);
+ setStackPointerRegisterToSaveRestore(SP::O6);
- if (TM.getSubtarget<SparcV8Subtarget>().isV9()) {
+ if (TM.getSubtarget<SparcSubtarget>().isV9()) {
setOperationAction(ISD::CTPOP, MVT::i32, Legal);
}
computeRegisterProperties();
}
-const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
+const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
default: return 0;
- case V8ISD::CMPICC: return "V8ISD::CMPICC";
- case V8ISD::CMPFCC: return "V8ISD::CMPFCC";
- case V8ISD::BRICC: return "V8ISD::BRICC";
- case V8ISD::BRFCC: return "V8ISD::BRFCC";
- case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC";
- case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC";
- case V8ISD::Hi: return "V8ISD::Hi";
- case V8ISD::Lo: return "V8ISD::Lo";
- case V8ISD::FTOI: return "V8ISD::FTOI";
- case V8ISD::ITOF: return "V8ISD::ITOF";
- case V8ISD::CALL: return "V8ISD::CALL";
- case V8ISD::RET_FLAG: return "V8ISD::RET_FLAG";
+ case SPISD::CMPICC: return "SPISD::CMPICC";
+ case SPISD::CMPFCC: return "SPISD::CMPFCC";
+ case SPISD::BRICC: return "SPISD::BRICC";
+ case SPISD::BRFCC: return "SPISD::BRFCC";
+ case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
+ case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
+ case SPISD::Hi: return "SPISD::Hi";
+ case SPISD::Lo: return "SPISD::Lo";
+ case SPISD::FTOI: return "SPISD::FTOI";
+ case SPISD::ITOF: return "SPISD::ITOF";
+ case SPISD::CALL: return "SPISD::CALL";
+ case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
}
}
/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
/// be zero. Op is expected to be a target specific node. Used by DAG
/// combiner.
-bool SparcV8TargetLowering::
+bool SparcTargetLowering::
isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask) const {
switch (Op.getOpcode()) {
default: return false;
- case V8ISD::SELECT_ICC:
- case V8ISD::SELECT_FCC:
+ case SPISD::SELECT_ICC:
+ case SPISD::SELECT_FCC:
assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!");
// These operations are masked zero if both the left and the right are zero.
return MaskedValueIsZero(Op.getOperand(0), Mask) &&
@@ -266,13 +266,13 @@ isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask) const {
/// either one or two GPRs, including FP values. TODO: we should pass FP values
/// in FP registers for fastcc functions.
std::vector<SDOperand>
-SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
+SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
SSARegMap *RegMap = MF.getSSARegMap();
std::vector<SDOperand> ArgValues;
static const unsigned ArgRegs[] = {
- V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
+ SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
};