1 files changed, 24 insertions, 2 deletions
diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp
index 01c513ac5e..6a60a66608 100644
--- a/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -21,16 +21,38 @@ SparcV8InstrInfo::SparcV8InstrInfo()
   : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])){
 }
 
+static bool isZeroImmed (const MachineOperand &op) {
+  return (op.isImmediate() && op.getImmedValue() == 0);
+}
+
 /// Return true if the instruction is a register to register move and
 /// leave the source and dest operands in the passed parameters.
 ///
 bool SparcV8InstrInfo::isMoveInstr(const MachineInstr &MI,
                                    unsigned &SrcReg, unsigned &DstReg) const {
-  if (MI.getOpcode() == V8::ORrr) {
-    if (MI.getOperand(1).getReg() == V8::G0) {  // X = or G0, Y -> X = Y
+  // We look for 3 kinds of patterns here:
+  // or with G0 or 0
+  // add with G0 or 0
+  // fmovs or FpMOVD (pseudo double move).
+  if (MI.getOpcode() == V8::ORrr || MI.getOpcode() == V8::ADDrr) {
+    if (MI.getOperand(1).getReg() == V8::G0) {
+      DstReg = MI.getOperand(0).getReg();
+      SrcReg = MI.getOperand(2).getReg();
+      return true;
+    } else if (MI.getOperand (2).getReg() == V8::G0) {
+      DstReg = MI.getOperand(0).getReg();
+      SrcReg = MI.getOperand(1).getReg();
+      return true;
+    }
+  } else if (MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) {
+    if (isZeroImmed (MI.getOperand (1))) {
       DstReg = MI.getOperand(0).getReg();
       SrcReg = MI.getOperand(2).getReg();
       return true;
+    } else if (isZeroImmed (MI.getOperand (2))) {
+      DstReg = MI.getOperand(0).getReg();
+      SrcReg = MI.getOperand(1).getReg();
+      return true;
     }
   } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD) {
     SrcReg = MI.getOperand(1).getReg();